76 papers
This paper proposes and validates a hardware-efficient, explainable Convolutional Tsetlin Machine (CTM) for real-time 5G jamming detection that achieves comparable accuracy to convolutional neural networks while significantly reducing training time, memory usage, and enabling deterministic FPGA deployment.
This paper introduces Orion, the first open end-to-end system that bypasses Apple's opaque CoreML framework to enable direct Neural Engine programming for large language model training and inference, achieving an 8.5x speedup in weight updates through a novel patching mechanism and demonstrating stable training of 110M-parameter models on Apple Silicon.
This paper proposes and analyzes optimized many-hypercube codes using smaller constituent blocks and efficient encoders to achieve lower logical error rates and reduced overhead, thereby facilitating the earlier experimental realization of high-rate fault-tolerant quantum computing.
This paper proposes Boundary Suppressed K-Means Quantization (BS-KMQ), a novel nonlinear quantization method that suppresses boundary outliers to optimize analog-to-digital converter resolution in in-memory computing, achieving significant improvements in quantization accuracy, area efficiency, and energy performance across various deep learning models.
This paper proposes a scalable and cost-efficient solution for Large Language Models by integrating Compute Express Link (CXL) memory pools into SGLang to store Engram conditional memory, achieving near-DRAM end-to-end performance while overcoming the latency limitations of traditional RDMA approaches.
This position paper reframes multi-agent memory as a computer architecture challenge by proposing a three-layer hierarchy and identifying critical protocol gaps, with a specific focus on resolving multi-agent memory consistency as the primary obstacle to building reliable and scalable collaborative systems.
This paper addresses the challenge of fluctuating decoder demand in quantum error correction by proposing a two-level framework managed by a quantum operating system that treats decoders as shared resources, thereby reducing hardware requirements by 10–40% and making fault-tolerant quantum computing more practical.
This paper presents a reference architecture and roadmap for Quantum-Centric Supercomputing (QCSC) systems that integrate quantum, GPU, and CPU resources to overcome current isolation challenges and enable seamless, high-performance hybrid workflows across three evolutionary phases.
HTM-EAR is a hierarchical tiered memory system that combines HNSW-based working memory with archival storage, importance-aware eviction, and hybrid routing to effectively preserve essential information and maintain high retrieval precision under sustained saturation, significantly outperforming traditional LRU approaches while approaching the performance of unbounded oracle memory.
This paper presents a comprehensive benchmark of production LLM inference on AMD Instinct MI325X GPUs, demonstrating that architecture-aware optimizations—specifically the selective use of the AITER runtime and specific KV cache configurations—are critical for maximizing throughput across diverse model families while maintaining high reliability under heavy concurrency.
This paper presents an efficient pipelined FPGA architecture with optimized memory organization for the displacement vector search module of JPEG XS's Intra Pattern Copy tool, achieving a throughput of 38.3 Mpixels/s at 277 mW to enable practical hardware deployment.
This paper introduces dmaplane, a Linux kernel module that provides explicit kernel-level buffer orchestration for high-performance AI data paths by integrating features like DMA lifecycle management, NUMA-aware allocation, and RDMA-based cross-device sharing to enable efficient, safe, and disaggregated AI inference.
RedFuser is an automatic framework that employs a formal theoretical methodology to identify and fuse cascaded reduction operations into optimized single-loop kernels, achieving significant speedups over state-of-the-art AI compilers while matching the performance of hand-written solutions.
This white paper presents a community-driven vision to prioritize research and development in hardware-based machine learning systems—leveraging emerging technologies like AI, silicon microelectronics, and quantum algorithms—to address the unprecedented data acquisition challenges and enable real-time scientific discovery in next-generation particle physics experiments.
This paper proposes a hardware-efficient "soft sparsity" paradigm for CNNs that utilizes a Most Significant Bit (MSB) proxy to skip negligible non-zero multiplications, achieving significant MAC and power reductions with zero accuracy loss while outperforming traditional zero-skipping methods.
This paper introduces "Linear Layouts," a novel framework that models tensor layouts as linear algebra operations over to enable generic, efficient, and bug-free layout definitions and conversions for deep learning workloads, successfully integrating with the Triton compiler to overcome the limitations of existing case-by-case approaches.
This paper proposes an Integrated Failure and Threat Mode and Effect Analysis (FTMEA) framework for automotive semiconductors that unifies functional safety and cybersecurity assessments by introducing quantified Cross-Domain Correlation Factors to accurately identify and prioritize synergistic risks that traditional methods often overlook.
This paper proposes a scalable digital compute-in-memory SRAM-based Ising machine that reformulates binary neural network robustness verification as a QUBO problem, leveraging imperfect solutions to efficiently detect adversarial perturbations while achieving significant improvements in convergence speed and power efficiency compared to conventional CPU implementations.
This paper presents an FPGA accelerator that eliminates the memory-bound bottleneck of Gated DeltaNet decode by persistently storing the full recurrent state in on-chip BRAM, achieving 4.5 faster inference and up to 60 higher energy efficiency compared to an NVIDIA H100 GPU.
This paper derives model-agnostic theoretical lower-bounds for the energy-to-solution metric of ideal neuromorphic learning-in-memory optimizers by analyzing their out-of-equilibrium thermodynamics, demonstrating how matching memory dynamics to optimization processes can overcome energy bottlenecks associated with memory writes and consolidation in large-scale AI workloads.