A 1.6-fJ/Spike Subthreshold Analog Spiking Neuron in 28 nm CMOS

This paper presents a 1.6-fJ/spike subthreshold analog Leaky Integrate-and-Fire neuron fabricated in 28 nm CMOS, which achieves a 300 kHz spiking frequency at 250 mV and demonstrates 82.5% accuracy on the MNIST dataset when used in a quantized Spiking Neural Network, validating its potential for energy-efficient embedded machine learning.

The Gist

Imagine your brain is a massive, bustling city where billions of tiny messengers (neurons) are constantly running around, shouting messages to each other. These messengers don't talk constantly; they only shout when they have something important to say. This "shout" is called a spike.

Because these messengers are so efficient—only talking when necessary—your brain uses very little energy compared to a supercomputer trying to do the same job. Scientists have been trying to build computer chips that work like this brain city for years. These chips are called Neuromorphic (meaning "brain-shaped") systems.

Here is the story of this paper, explained simply:

1. The Problem: The Energy Hungry Computer

Right now, if you want to run smart AI on your phone or a medical implant, the computer chips inside are like gas-guzzling trucks. They are heavy, they get hot, and they drain your battery quickly. They are trying to simulate the brain using "digital" math (1s and 0s), which is like trying to run a marathon by taking tiny, stiff steps instead of a natural stride.

2. The Solution: A Tiny, Ultra-Efficient Messenger

The team in this paper built a new type of computer chip component: a single artificial neuron. Think of this neuron as a tiny, ultra-efficient messenger designed to live on a microchip.

• The Size: It is incredibly small. If you zoomed in, it would take up less space than a single grain of sand. In fact, it's so small that you could fit millions of them on a chip the size of a fingernail.
• The Energy: This is the magic part. Every time this tiny messenger "shouts" (fires a spike), it uses 1.61 femtojoules of energy.
  • Analogy: A femtojoule is to a joule what a single drop of water is to the entire Atlantic Ocean. It is so little energy that it's almost nothing. To put it in perspective, this chip uses less energy to fire a signal than a mosquito uses to flap its wings once.

3. How It Works: The "Leaky Bucket"

The scientists used a model called Leaky Integrate-and-Fire (LIF). Imagine a bucket with a small hole in the bottom (a leak).

• Integrate: You pour water (signals from other neurons) into the bucket.
• Leak: Because of the hole, the water slowly drains out.
• Fire: If you pour water fast enough to fill the bucket before it leaks out, the bucket overflows. That overflow is the "spike" or the message being sent.
• Reset: Once it overflows, the bucket is instantly emptied and ready to catch water again.

The team built this "bucket" using transistors (tiny switches) on a silicon chip. They made the bucket so small and the hole so precise that it works perfectly even when the "water pressure" (voltage) is extremely low.

4. The Big Test: Can It Think?

Building a single messenger is cool, but can a whole team of them solve a problem?

• The team took the measurements from their physical chip and created a software simulation of it.
• They taught this simulated brain to recognize handwritten numbers (like the digits 0–9) using a famous dataset called MNIST.
• The Result: It got about 82.5% accuracy.
  • Context: While a human gets 99%+ accuracy, this is a huge success for a tiny, low-power chip that mimics real brain physics. It proves that this tiny, energy-starved messenger can actually learn and do useful work.

5. Why This Matters: The Future of "Edge AI"

This research is a breakthrough for Edge AI (smart devices that work without needing the internet).

• Medical Implants: Imagine a pacemaker or a cochlear implant that can process complex signals in real-time without needing to be recharged every day. This chip uses so little power it could run for years on a tiny battery.
• Tiny Robots: A robot ant or a drone could have a "brain" that lets it react instantly to its environment without a heavy battery pack.
• Smartphones: Your phone could recognize your voice or face using a fraction of the battery it uses today.

Summary

The authors built the smallest, most energy-efficient "brain cell" ever made on a computer chip. It's like shrinking a gas-guzzling truck down to the size of a bicycle, but making it just as fast and capable of carrying a heavy load. By proving this works in real hardware and can learn simple tasks, they've paved the way for a future where our devices are smarter, smaller, and last much longer on a single charge.

Technical Summary

Here is a detailed technical summary of the paper "A 1.6-fJ/Spike Subthreshold Analog Spiking Neuron in 28 nm CMOS."

1. Problem Statement

Deep learning algorithms face significant challenges regarding speed and memory requirements, particularly for energy-constrained portable devices and edge AI applications. While digital neuromorphic processors exist, they often lack the extreme energy efficiency of biological systems. Existing analog spiking neuron implementations face a trade-off: they either consume too much energy (picojoules to nanojoules per spike) or occupy too much silicon area, limiting their scalability for large-scale Spiking Neural Networks (SNNs) on portable or implantable platforms. There is a critical need for ultra-low-power, high-density analog neuron building blocks that can operate at sub-threshold voltages (<300 mV) with sub-femtojoule energy per event.

2. Methodology

The authors designed, fabricated, and characterized a Leaky Integrate-and-Fire (LIF) neuron using TSMC 28 nm CMOS technology.

• Circuit Architecture:

  • Integration Block: Utilizes a current mirror (M1-M2) and a membrane capacitor ($C_{mem}$) to integrate synaptic input currents ($I_{syn}$).
  • Leak Pathway: Implemented implicitly through the sub-threshold operation of transistors M3 and M4, eliminating the need for large on-chip resistors and saving area.
  • Spike Generation: A two-stage inverter chain (M5-M8) acts as a comparator. When the membrane voltage ($V_{mem}$) crosses a threshold, it triggers a spike.
  • Reset Mechanism: A dedicated reset block (M3-M4 and $C_{res}$) discharges $C_{mem}$ and resets the membrane potential to $V_{reset}$ after a spike, including a refractory period.
  • Operation Mode: The circuit operates in deep sub-threshold at a supply voltage of 250 mV, leveraging exponential current-voltage characteristics to minimize power.

• Fabrication and Testing:

  • The design was fabricated in a 28 nm process.
  • 20 ASIC samples were packaged (DIP20) and tested on a custom PCB.
  • Characterization: Input currents were generated using a Keithley picoammeter. Membrane voltage and spike outputs were monitored via internal analog buffers and an oscilloscope.
  • Co-Simulation: A hybrid approach combined post-layout simulations with experimental measurements to accurately infer input synaptic currents at the picoampere level.

• Software Emulation:

  • A software model was developed in PyTorch using the measured firing rate vs. input current ($f-I$) curves from the hardware.
  • The model was trained on the MNIST dataset using surrogate gradient techniques to handle the non-differentiability of spike functions.
  • Post-Training Quantization (PTQ) was applied to reduce weights to 4-bit precision to simulate resource-constrained edge environments.

3. Key Contributions

• Record-Breaking Efficiency: The design achieves an energy consumption of 1.61 fJ/spike with an active area of only 34 µm².
• Low-Voltage Operation: The neuron operates effectively at a supply voltage of 250 mV, a regime rarely explored in analog CMOS neurons which typically require higher voltages.
• Scalability: The compact footprint and low energy consumption make this architecture a viable candidate for large-scale Neuromorphic Systems-on-Chip (NeuroSoC).
• Hardware-Software Co-Validation: The paper bridges the gap between silicon and software by validating the hardware characteristics through a software model that successfully trains an SNN on MNIST, demonstrating end-to-end feasibility.

4. Key Results

• Energy & Area:
  • Energy per Spike: 1.61 fJ (minimum measured at 1500 pA input current).
  • Active Area: 34 µm².
  • Supply Voltage: 250 mV.
• Performance:
  • Max Spiking Frequency: 300 kHz.
  • Input Range: Operates with input synaptic currents from 10 pA to 10 nA.
  • Leakage: Gate leakage currents are negligible (100 fA to 1 pA) compared to signal currents.
• Software Simulation (MNIST):
  • Using a [400-128-10] network topology with 4-bit quantization, the model achieved 82.5% test accuracy.
  • The average energy per inference was estimated at 483 pJ (based on hardware spike energy).
• Comparative Analysis:
  • Compared to previous works (e.g., Indiveri et al., 2006; Ferreira et al., 2019), this work offers a superior balance of energy density and area. It significantly outperforms older 65 nm and 0.35 µm implementations in both energy and footprint.

5. Significance

This work represents a significant step forward in TinyML and EdgeAI. By demonstrating that a sub-femtojoule, sub-300 mV analog neuron can be successfully fabricated in a modern 28 nm node, the authors prove that high-density, ultra-low-power neuromorphic hardware is achievable.

• Impact on Edge AI: The extreme energy efficiency allows for the deployment of complex SNNs on battery-powered devices and biomedical implants where power is scarce.
• Design Paradigm: The implicit leak implementation and sub-threshold operation provide a blueprint for future analog circuit designers aiming to minimize silicon footprint and power dissipation.
• Future Outlook: While the current work focuses on the neuron cell (excluding synaptic integration), it establishes a robust foundation for building full-scale NeuroSoCs. Future work will focus on integrating synaptic circuits (e.g., memristors) and utilizing more efficient coding schemes (spike-latency) to further reduce energy consumption.

In conclusion, this paper validates a scalable, high-performance analog LIF neuron that sets a new benchmark for energy efficiency and area density in neuromorphic computing.