ChipletPart: Cost-Aware Partitioning for 2.5D Systems

This paper introduces ChipletPart, a cost-driven 2.5D system partitioner that integrates a sophisticated cost model with genetic algorithm-based technology assignment and simulated annealing floorplanning to significantly reduce chiplet costs and ensure I/O feasibility compared to state-of-the-art methods.

The Gist

Imagine you are a master chef trying to build the world's most delicious, complex banquet. In the past, you had to cook the entire meal on one giant, single stove (a monolithic chip). If the stove was too big, it was expensive to build, and if one part burned, the whole meal was ruined.

Now, technology has evolved. Instead of one giant stove, you can use a 2.5D system: a large, high-tech serving tray (the interposer) where you place several smaller, specialized cooking stations (chiplets). You can put a high-performance gas burner for the steak (the CPU) and a gentle electric oven for the soufflé (the memory) right next to each other.

But here's the problem: How do you decide which ingredients go on which station?

If you put the steak and the soufflé too far apart, the steam (data) takes too long to travel, and the food gets cold. If you put them too close, the heat from the burner might burn the soufflé. Also, some stations are expensive to build, while others are cheap. You want the best meal for the lowest price, without burning anything.

This is exactly what the paper "ChipletPart" solves. It introduces a smart, automated "Head Chef" (an algorithm) that figures out the perfect way to chop up a giant design into smaller chiplets to save money and ensure everything fits together perfectly.

Here is a simple breakdown of how it works:

1. The Problem: The "Cut-and-Paste" Mistake

Old methods of splitting up these designs were like using a dull knife to cut a cake. They just tried to make sure the pieces were roughly the same size (min-cut partitioning). They didn't care if the pieces were actually edible (feasible) or if they were too expensive to bake.

• The Result: You might get a design that looks good on paper but is impossible to build because the wires connecting the chiplets are too long, or the cost is way too high.

2. The Solution: The "Smart Head Chef" (ChipletPart)

The authors created ChipletPart, a tool that acts like a super-intelligent planner. It doesn't just cut the cake; it tastes every slice before you bake it.

It uses three main tricks:

A. The "Cost Calculator" (The Budget)

ChipletPart knows that not all cooking stations are created equal.

• Some are High-End (expensive, fast, like a 3nm process).
• Some are Budget (cheaper, slower, like a 14nm process).
• The Magic: It figures out that you should cook the "steak" on the expensive High-End station because it needs speed, but cook the "rice" on the cheap Budget station because it doesn't need to be fast. This is called Heterogeneous Integration. It mixes and matches different technologies to save money, just like buying premium ingredients only where they matter.

B. The "Wire Length" Rule (The Reach)

Imagine your cooking stations are connected by hoses. If the hose is too short, the water won't reach. In chip design, this is called I/O Reach.

• ChipletPart checks the "hose length" constantly. If it tries to put two stations too far apart, it knows the hose won't reach, and it immediately says, "No, move them closer!"
• It uses a technique called Simulated Annealing (think of it as a "trial-and-error" dance) to shuffle the chiplets around on the tray until they fit perfectly without breaking any hoses.

C. The "Evolutionary Chef" (Genetic Algorithm)

How does it find the best arrangement among billions of possibilities?

• It uses a Genetic Algorithm. Imagine it creates 50 different "draft menus" (partitions).
• It tastes them all. The ones that are too expensive or have broken hoses get thrown out.
• It takes the best two menus, mixes their recipes together (crossover), and adds a little random spice (mutation) to create new, potentially better menus.
• It repeats this process over and over, evolving the design until it finds the absolute cheapest, most feasible solution.

3. The Results: Saving the Bank

The paper tested this "Head Chef" against other methods and even human experts. The results were impressive:

• Cheaper: It cut costs by up to 58% compared to old methods. That's like turning a $1,000 dinner into a $420 dinner with the same quality.
• Feasible: Unlike other tools that often propose impossible designs, ChipletPart always ensures the design can actually be built (the hoses always reach).
• Smarter: It found that mixing different technologies (using both expensive and cheap stations) saved up to 43% compared to using just one type of station for everything.

4. The "Secret Sauce" (Bayesian Optimization)

The authors also tried a different method called Bayesian Optimization. Think of this as a "Gourmet Consultant" who is incredibly smart but very slow.

• It can sometimes find a slightly better solution (saving another 5% cost), but it takes 4 times longer to do the math.
• So, the authors say: Use the "Genetic Algorithm" (the fast, reliable Head Chef) for most jobs, and only call in the "Gourmet Consultant" if you have a very specific, difficult problem and unlimited time.

Summary

ChipletPart is a new, open-source tool that helps engineers design the next generation of super-computers and smartphones. Instead of guessing how to split a giant chip into smaller pieces, it uses smart math to:

1. Mix and match different manufacturing technologies to save money.
2. Shuffle the pieces until they fit together perfectly without breaking the connections.
3. Guarantee that the final design is actually buildable and affordable.

It's like having a robot chef that ensures your banquet is not only delicious but also the cheapest possible to make, without burning a single dish.

Technical Summary

Here is a detailed technical summary of the paper "ChipletPart: Cost-Aware Partitioning for 2.5D Systems".

1. Problem Statement

The integration of chiplets in 2.5D systems offers a cost-effective path to building large, high-performance systems by enabling heterogeneous manufacturing technologies and improving yield. However, partitioning a large monolithic design into chiplets is a complex optimization problem that differs fundamentally from traditional netlist min-cut partitioning.

Key Challenges:

• Complex Objective Function: The goal is not merely to minimize the number of cut nets (cutsize) but to minimize the total system cost, which includes Non-Recurring Engineering (NRE), recurring manufacturing (NRE), assembly, yield, and interposer costs.
• I/O Reach Constraints: Inter-chiplet communication is limited by the physical reach of I/O transceivers (e.g., UCIe limits). A partition is only valid if the physical distance between connected chiplets does not exceed the I/O reach. Traditional partitioners often ignore this, leading to floorplan-infeasible solutions.
• Heterogeneous Technology Assignment: Different chiplets can be manufactured on different process nodes (e.g., 7nm, 10nm, 14nm). Assigning the optimal technology to each chiplet is a combinatorial problem that significantly impacts cost and performance.
• Granularity: The problem operates at the block/IP level (hundreds of blocks), not the gate level, requiring a different approach than standard EDA tools.

2. Methodology: The ChipletPart Framework

The authors propose ChipletPart, an open-source, unified framework that integrates cost-driven partitioning, heterogeneous technology assignment, and I/O-reach-aware floorplanning. The framework employs a modular optimization approach combining Genetic Algorithms (GA) and Simulated Annealing (SA).

A. Overall Architecture

The framework operates in an iterative loop:

1. Genetic Algorithm (GA) for Technology Assignment:

   • Genome: A sequence of technology nodes assigned to the chiplets.
   • Process: The GA evolves populations of technology assignments. It uses tournament selection, uniform crossover, and mutation to explore the trade-offs between different process nodes (e.g., placing logic on a cheaper node and memory on a more advanced one).
   • Role: Handles the discrete, combinatorial aspect of assigning manufacturing technologies to partitions.

2. Core-ChipletPart (Partitioning & Refinement):

   • Initial Pool Generation: Generates a diverse pool of initial partitions using Spectral Partitioning, High-Degree Node Expansion, Random Partitioning, and METIS.
   • Pruning: Uses statistical filtering (Z-score and relative cost thresholds) to discard low-quality initial solutions.
   • Refinement: Applies Fiduccia-Mattheyses (FM) and Kernighan-Lin (KL) algorithms. Crucially, every move or swap triggers a cost evaluation that includes a floorplan check.

3. Reach-Aware Simulated Annealing (SA) Floorplanner:

   • Input: A set of chiplets and their connectivity.
   • Objective: Minimize a weighted sum of reach violation penalties, chiplet area, and package area.
   • Mechanism: Uses Sequence Pairs to represent spatial arrangements. It employs five perturbation operators:
     • Swapping chiplets in sequence pairs.
     • Reshaping chiplets (resizing) to align boundaries.
     • Expanding (bloating) chiplets into whitespace to satisfy reach constraints without moving them.
   • Go-With-the-Winners (GWTW): A parallelization strategy where 10 SA walkers explore the space, periodically synchronizing to clone the best solutions, balancing exploration and exploitation.

4. Cost Model:

   • The framework uses a sophisticated, open-source cost model (ported from Python to C++ for a 5x–100x speedup) that calculates costs based on die area, yield, assembly, NRE, and I/O overhead.

B. Alternative Optimizer: Bayesian Optimization (BO)

The paper also explores Bayesian Optimization as an alternative to GA.

• Approach: Uses spectral embeddings to create a continuous relaxation of the discrete partitioning problem. It optimizes centroids in a spectral space and technology assignments (encoded as one-hot vectors).
• Trade-off: BO can find slightly better solutions (up to 5.3% improvement) on specific large designs but incurs a 2x–4x runtime overhead compared to GA.

3. Key Contributions

1. Unified Framework: First open-source tool to jointly optimize partitioning, heterogeneous technology assignment, and I/O-feasible floorplanning.
2. I/O-Feasibility Guarantee: Unlike standard min-cut partitioners (e.g., hMETIS, TritonPart) or prior tools (Floorplet, Chipletizer) that often produce infeasible solutions, ChipletPart guarantees that all generated partitions satisfy I/O reach constraints via its SA-based floorplanner.
3. Heterogeneous Integration: Explicitly models and optimizes the assignment of different process nodes to different chiplets during the partitioning phase, a capability missing in existing tools.
4. Performance & Scalability:
   • Ported the cost model to C++, achieving a 100x speedup over Python-based implementations.
   • Handles large-scale designs (up to ~384 IP blocks) with runtimes under two hours.
5. Open Ecosystem: The tool, cost model, and a standardized set of benchmarks (including scaled industry designs like EPYC and GA100) are released as open source.

4. Experimental Results

The authors evaluated ChipletPart against state-of-the-art (SOTA) tools (hMETIS, TritonPart, Floorplet, Chipletizer) and manual partitions across nine diverse testcases.

• Cost Reduction vs. Min-Cut Partitioners: ChipletPart reduces chiplet cost by up to 58% (20% geometric mean) compared to hMETIS and TritonPart. These SOTA tools often produce solutions that are infeasible due to I/O reach violations.
• Cost Reduction vs. Prior Art:
  • vs. Floorplet: Up to 47% lower cost (6% geometric mean). Floorplet sometimes produces lower nominal costs but fails feasibility checks.
  • vs. Chipletizer: Up to 48% lower cost (30% geometric mean). Chipletizer failed to produce solutions for several large testcases due to scalability issues.
• Heterogeneous Benefits: Using heterogeneous technology assignment reduces cost by up to 43% (15% geometric mean) compared to homogeneous implementations.
• Human Baseline: ChipletPart generates solutions 34% better (13% geometric mean) than manual partitions created by engineers.
• Feasibility: ChipletPart consistently produces I/O-feasible solutions across all testcases, whereas other methods frequently fail (e.g., hMETIS and TritonPart failed feasibility in 5/9 and 3/9 cases respectively).

5. Significance and Impact

• Bridging the Gap: ChipletPart addresses the critical gap between logical partitioning and physical implementation in 2.5D systems. By ensuring floorplan feasibility early in the design flow, it prevents costly redesigns later.
• Economic Optimization: It shifts the focus from simple connectivity minimization to holistic system cost minimization, accounting for the complex economics of heterogeneous manufacturing and packaging.
• Design Space Exploration: The tool enables designers to rapidly explore the impact of packaging technologies (e.g., UCIe vs. parallel I/O), I/O reach limits, and process node mixtures on system architecture.
• Community Resource: By providing a standardized, open-source benchmark suite and tool, the authors facilitate reproducible research and further development in the emerging field of chiplet-based design.

In conclusion, ChipletPart represents a significant advancement in 2.5D system design automation, offering a robust, cost-driven, and physically feasible solution for partitioning complex heterogeneous systems.