Mapping the positions of Two-Level-Systems on the surface of a superconducting transmon qubit

This paper presents a method to map the individual positions of surface two-level-systems (TLS) on a superconducting transmon qubit by utilizing local electric fields from on-chip gate electrodes, revealing that TLS density is significantly enhanced near the Josephson junction leads rather than the larger capacitor area, thereby guiding future qubit design and fabrication improvements.

The Gist

Imagine you are trying to keep a perfectly balanced spinning top (a superconducting qubit) spinning for as long as possible. This top is the brain of a future quantum computer. But there's a problem: invisible, microscopic "gremlins" are constantly bumping into it, causing it to wobble and stop. These gremlins are called Two-Level Systems (TLS).

For years, scientists knew these gremlins existed and were ruining the computer's performance, but they didn't know where they were hiding or what they looked like. They were like ghosts in the machine—everywhere and nowhere at once.

This paper is about a team of scientists who finally built a "ghost hunter" to find exactly where these gremlins are hiding on their quantum chip.

The Problem: The Invisible Gremlins

Think of the quantum chip as a tiny city made of metal roads and bridges. The "gremlins" (TLS) are defects in the material—tiny atoms that got stuck in the wrong place or are jiggling between two spots. When the quantum computer tries to do math, these gremlins absorb energy and cause the computer to lose its memory (decoherence).

The big mystery was: Are the gremlins hiding in the big open squares of the city, or are they clustered in the narrow alleyways?

The Solution: The "Electric Flashlight"

The scientists built a special transmon qubit (the spinning top) surrounded by four tiny gate electrodes. You can think of these electrodes as four powerful flashlights that can shine a specific kind of "electric light" (a DC electric field) onto different parts of the chip.

Here is how they caught the gremlins:

1. The Tuning Trick: Every gremlin has a favorite frequency (like a radio station). If you shine the right amount of electric light on a gremlin, you can change its radio station.
2. The Listening Game: The scientists slowly turned up the voltage on each of the four flashlights one by one.
3. The Reaction: When a flashlight hit a gremlin, the gremlin would "sing" (change its frequency). The scientists listened for this song by watching how quickly the spinning top stopped spinning.
4. Triangulation: This is the clever part.
   • If a gremlin is right next to Flashlight A, it will react strongly to Flashlight A and weakly to Flashlight B.
   • If it's in the middle, it reacts somewhat equally to both.
   • By comparing how loudly the gremlin "sang" in response to each of the four flashlights, the scientists could use a process called triangulation (just like how your phone finds your location using cell towers) to pinpoint the gremlin's exact coordinates on the map.

The Big Discovery: The "Shadowy" Alleyways

Once they mapped out the locations of 55 different gremlins, they found something surprising.

• The Expectation: They thought the gremlins would be spread out evenly, mostly in the big, open areas (the capacitor) because that's where most of the electric energy lives.
• The Reality: 58% of the gremlins were hiding in the tiny, narrow leads of the Josephson Junctions (the tiny bridges connecting parts of the circuit).

Why?
The scientists realized it was about how the city was built.

• The big open areas were built using a "subtractive" method (like carving a statue out of a block of stone). This is clean and smooth.
• The tiny junction leads were built using a "lift-off" method (like pouring concrete into a mold and then peeling the mold away). This process leaves behind tiny, messy residues and rough edges—perfect hiding spots for gremlins.

It's like finding that all the trash in a city isn't in the parks, but is piled up specifically in the alleyways behind the buildings because that's where the garbage trucks drop off the bags.

Why This Matters

This isn't just about finding bugs; it's about fixing the blueprint.

1. Better Design: Now that we know the gremlins love the "lift-off" construction method, engineers can change how they build these chips. They can smooth out those alleyways or use different construction techniques to keep the gremlins away.
2. Targeted Cleaning: Instead of trying to clean the whole city, they can now focus their cleaning efforts on the specific "hotspots" where the gremlins gather.
3. Active Control: Since they can "talk" to the gremlins with the electric flashlights, they might eventually be able to tune the gremlins so they stop interfering with the computer's work, effectively silencing the noise.

The Bottom Line

This paper is a breakthrough because it moved from guessing where the problems are to seeing them on a map. By using electric fields as a flashlight and triangulation as a GPS, the scientists proved that the biggest enemies of quantum computers aren't random; they are hiding in specific, predictable places caused by how we manufacture the chips. This gives engineers a clear roadmap to build faster, more reliable quantum computers in the future.

Technical Summary

Here is a detailed technical summary of the paper "Mapping the positions of Two-Level-Systems on the surface of a superconducting transmon qubit."

1. Problem Statement

Superconducting quantum computers suffer from limited coherence times primarily due to Two-Level Systems (TLS). These are atomic-scale defects in amorphous materials (such as surface oxides, photoresist residues, or tunnel barriers) that act as parasitic quantum systems.

• The Challenge: While TLS are known to be the dominant source of dielectric loss, their microscopic nature, exact locations, and specific contribution to decoherence in different parts of a qubit circuit remain poorly understood.
• The Limitation: Standard methods (like measuring quality factors in resonators) provide ensemble averages but cannot pinpoint individual TLS locations. In qubits, coherence is often limited by just a few strongly coupled, near-resonant TLS, making ensemble averaging insufficient for targeted design improvements.
• The Goal: To develop a method to map the individual spatial positions of surface TLS on a transmon qubit to identify "hotspots" of defect density and guide fabrication improvements.

2. Methodology

The authors developed a spatial trilateration method using on-chip gate electrodes to manipulate and locate individual TLS.

• Device Design:

  • A standard XMon transmon qubit was fabricated on a sapphire substrate using aluminum.
  • The design integrates four DC gate electrodes ($\alpha, \beta, \gamma, \delta$) placed in close proximity to the qubit island and Josephson junction leads.
  • These electrodes generate localized, spatially varying DC electric fields ($E_{DC}$) when biased with specific voltages.

• Physical Principle:

  • Charged TLS possess an electric dipole moment ($p$). Their resonance frequency ($\omega_{TLS}$) depends on the local electric field via the Stark effect:
    $$\omega_{TLS} = \frac{1}{\hbar}\sqrt{\Delta^2 + (\varepsilon + 2p \cdot E)^2}$$
    where $\Delta$ is the tunneling energy and $\varepsilon$ is the asymmetry energy.
  • By applying voltages to the gate electrodes, the researchers tune the TLS resonance frequencies.

• Detection Protocol (TLS Swap Spectroscopy):

  • The qubit is excited and tuned to various frequencies to interact with TLS.
  • When the qubit frequency resonates with a TLS, energy is exchanged, causing a measurable dip in the qubit's energy relaxation time ($T_1$).
  • The voltages on the four gate electrodes are swept to trace the hyperbolic resonance curves of individual TLS.

• Localization Algorithm:

  • The tuning strength ($\gamma_i$) of a TLS to each electrode $i$ is extracted by fitting the resonance traces.
  • Since the absolute dipole moment ($p$) is unknown, the method uses relative tuning ratios ($\gamma_i / \gamma_j$).
  • The authors simulate the DC electric field distribution ($E_i(x,y)$) for each electrode.
  • They search for the position $(x,y)$ where the ratio of simulated electric fields matches the measured ratio of tuning strengths:
    $$\frac{E_i(x,y)}{E_j(x,y)} \approx \frac{\gamma_i}{\gamma_j}$$
  • A cost function ($\sigma$) minimizes the difference between measured and simulated ratios across all electrode pairs to pinpoint the most probable TLS location.
  • Constraint: The algorithm restricts solutions to regions where the qubit's AC electric field ($|E_{rms}|$) is strong enough to couple to the TLS (detectability threshold).

3. Key Contributions

1. Spatial Mapping Technique: The first demonstration of a method to map the individual positions of surface TLS on a functional superconducting qubit without mechanical scanning (unlike scanning gate microscopy).
2. Identification of Fabrication Hotspots: The study reveals that TLS density is not uniform but significantly enhanced in specific fabrication regions.
3. Quantitative Dipole Moments: The method allows for the estimation of individual TLS electric dipole moments and coupling strengths.
4. Validation of Trilateration: The paper validates that the electric fields from the gate electrodes are sufficiently parallel near the qubit edges to allow the cancellation of the dipole moment vector in the localization equations.

4. Key Results

• TLS Distribution:
  • Out of 55 detected TLS, 58% were located on the leads of the Josephson junctions (DC-SQUID).
  • Only 27% were found on the capacitor island, and 14% on the ground plane.
• Fabrication Insight:
  • The Josephson junction leads are fabricated using shadow evaporation and lift-off techniques, whereas the capacitor island and ground plane are defined by subtractive dry etching.
  • The high concentration of TLS on the junction leads suggests that the lift-off process introduces significantly higher defect densities (likely due to resist residues, surface roughness, or grain boundaries) compared to etched structures.
  • The data implies the TLS density near the SQUID is approximately 2 times higher than in the rest of the circuit.
• TLS Properties:
  • The median electric dipole moment was estimated at $p_{\parallel} \approx 1.12 \pm 0.12 \, e\text{\AA}$, consistent with previous studies.
  • The spatial resolution of the mapping is estimated to be ~6 µm, limited by the steepness of the electric field gradients and measurement noise.
• Detection Limits:
  • TLS are only detectable within ~1–2 µm of electrode edges where the AC field is strong enough to cause a measurable $T_1$ reduction.

5. Significance and Impact

• Guiding Fabrication: The results provide direct evidence that lift-off processes are a critical bottleneck for qubit coherence. This suggests that switching to subtractive etching for junction leads or optimizing lift-off residues could drastically improve $T_1$ times.
• Design Optimization: The method identifies that the Josephson junction leads, despite having a smaller surface area than the capacitor, are the dominant source of loss due to their high electric field participation and high defect density. This advocates for wire-tapering techniques to dilute electric fields in these critical regions.
• Scalability: The technique is applicable to various qubit types (flux, phase, transmon) and can be integrated into flip-chip architectures. It enables active decoherence suppression by tuning specific dominant TLS out of resonance using the gate electrodes.
• Future Directions: This approach opens a pathway to systematically study the impact of different materials, contaminants, and processing steps on TLS formation, which is vital for the development of large-scale, fault-tolerant quantum processors.

In summary, this paper moves beyond statistical loss measurements to provide a microscopic, spatially resolved map of quantum defects, directly linking specific fabrication techniques (lift-off vs. etching) to qubit performance degradation.