Hardware-Aware Design of a GNN-Based Hit Filtering Algorithm for the Belle II Level-1 Trigger

This paper presents a hardware-aware model-compression workflow for a GNN-based hit-filtering algorithm deployed on FPGAs in the Belle II Level-1 trigger, achieving a reduction in computational cost by over two orders of magnitude through techniques like 4-bit fixed-point arithmetic and pruning while maintaining high hit efficiency and background rejection performance.

The Gist

Imagine you are running a massive, high-speed train station (the Belle II experiment) where millions of passengers (particles) arrive every second. Your job is to spot the VIPs (rare physics events) among the crowd.

The problem? The station is getting so crowded with "noise" (background radiation) that your security guards (the trigger system) are overwhelmed. They have a strict rule: they must decide who to let through in less than the blink of an eye (5 microseconds). If they are too slow, the data backs up, and the train stops. If they are too careless, they let too much junk through, clogging the system.

To solve this, the scientists built a super-smart AI security guard (a Graph Neural Network or GNN) that can instantly look at the crowd, figure out who is a VIP and who is just a tourist, and filter out the noise.

However, there's a catch: This AI is currently too "heavy" and "complex" to fit inside the tiny, specialized security booth (an FPGA chip) that needs to make these decisions in real-time. It's like trying to fit a supercomputer into a wristwatch.

The Solution: The "Hardware-Aware" Makeover

This paper describes how the team took their heavy, high-precision AI and gave it a radical, hardware-friendly makeover so it could fit into the tiny security booth without losing its ability to spot the VIPs. They did this through a four-step "diet and training" plan:

1. Shrinking the Brain (Model & Graph Reduction)

• The Analogy: Imagine the AI is a detective with a massive notebook of clues. It was writing down every single detail about every person in the station.
• The Fix: The team told the AI, "Stop writing everything down. Just focus on the most important clues." They reduced the number of "neurons" (the detective's brain cells) and stopped looking at connections in both directions (like only looking at people walking toward you, not away).
• Result: The AI became much smaller and faster, but still smart enough to do the job.

2. Switching to "Rough Draft" Math (4-Bit Quantization)

• The Analogy: The original AI was a perfectionist accountant who calculated everything down to the 10th decimal place using a giant calculator. This takes a long time and uses a lot of power.
• The Fix: The team told the AI, "You don't need to be that precise. Just use whole numbers and round off the decimals." They switched the AI from using high-precision "floating-point" math to "fixed-point" math (like using a slide rule instead of a supercomputer).
• Result: The calculations became incredibly fast and required much less energy, with almost no loss in accuracy.

3. Cutting the Dead Weight (Pruning)

• The Analogy: Imagine the detective's notebook has 100 pages, but 65 of them are just blank or contain useless scribbles.
• The Fix: The team went through the AI and ruthlessly cut out 65% of the connections that weren't actually helping it make decisions.
• Result: The AI became lean and mean, processing only the essential information.

4. The "Bit Operation" Scorecard

• The Analogy: To prove their new AI would fit in the tiny security booth, they needed a way to measure how much "work" it would do. They invented a score called Bit Operations (BOPs). Think of this as counting how many tiny steps the AI takes to solve a puzzle.
• The Result: The original AI took 116 million steps to check a crowd. The new, compressed AI only takes 1.8 million steps. That's a reduction of over 100 times!

Did it work?

Yes! The team tested the new, tiny AI on real data from the Belle II experiment.

• Performance: The original AI was 97.4% accurate at spotting VIPs. The new, compressed AI was 96.8% accurate. That's a tiny drop, but totally acceptable.
• Speed: The new AI fits perfectly into the tiny security booth (the FPGA chip). It processes the data in 632 nanoseconds, which is well under the 5-microsecond deadline.

The Bottom Line

The scientists successfully took a heavy, slow, high-precision AI and transformed it into a lightweight, lightning-fast version that can run on a tiny chip. They did this by making the AI "simpler," "rougher" in its math, and "leaner" by cutting out the fat.

Now, the Belle II experiment can filter out the noise in real-time, allowing them to catch those rare, precious physics events without getting bogged down by the crowd. It's a perfect example of software-hardware co-design: building the software specifically to fit the hardware it lives on.

Technical Summary

1. Problem Statement

The Belle II experiment at the SuperKEKB collider operates at high luminosity, generating significant beam-induced background. To manage data throughput, the experiment relies on a hardware Level-1 (L1) trigger system with strict constraints:

• Latency: Must operate within a 5 µs budget.
• Bandwidth: Must significantly reduce data volume before the Data Acquisition (DAQ) system.
• Hardware: The Central Drift Chamber (CDC) sub-trigger must process up to 978 sense wires per sector within a sub-microsecond latency budget using FPGA devices (specifically AMD Ultrascale XCVU190).

The core challenge is to implement a sophisticated Graph Neural Network (GNN) for hit filtering (distinguishing signal hits from background) on these resource-constrained FPGAs without sacrificing physics performance (efficiency and background rejection) or exceeding latency limits. Standard full-precision GNNs are too computationally expensive for this environment.

2. Methodology

The authors propose a software-hardware co-design workflow that iteratively adapts a full-precision GNN model for FPGA deployment. The process involves four main stages:

A. Baseline Model Architecture

• Architecture: A lightweight Interaction Network (a type of GNN) consisting of three Multi-Layer Perceptron (MLP) blocks:
  1. Edge Block ($R_1$): Updates edge features based on node inputs.
  2. Node Block ($O$): Aggregates edge features (via max-scatter) and updates node features.
  3. Final Edge Block ($R_2$): Classifies edges and aggregates results (via mean-scatter) to produce node-level scores.
• Input Graph: Constructed from CDC hits where sense wires are nodes. Edges connect wires based on pattern-based neighbors. Features include wire positions ($x, y$), ADC sums, and spatial/temporal differences ($\Delta r, \Delta \phi, \Delta TDC$).
• Baseline Specs: 3 hidden layers per MLP block with dimensions $[8,8,3]$, $[8,8,3]$, and $[8,8,1]$, totaling 495 trainable parameters.

B. Compression Pipeline

To fit the model into FPGA resources, the authors applied a sequence of optimizations:

1. Model & Graph Size Reduction:
   • Reduced hidden layers per MLP from 2 to 1.
   • Reduced hidden layer width from 8 to 6 neurons.
   • Result: Parameters reduced from 495 to 211.
   • Switched graph edges from bidirectional to unidirectional, halving the edge count and computational load.
2. 4-bit Quantization (Quantization-Aware Training):
   • Used Brevitas to replace floating-point layers with differentiable quantized equivalents.
   • Precision Scheme: 4-bit weights and inputs, 6-bit activations, 16-bit biases, and 8-bit outputs.
   • Removed the final sigmoid activation post-training (replaced by thresholding) to save resources.
3. Unstructured Pruning:
   • Applied iterative magnitude-based pruning, increasing sparsity linearly over training epochs.
   • Final Sparsity: 65%.

C. Hardware-Aware Complexity Metric

Instead of relying solely on FLOPs, the authors used Bit Operations (BOPs) as a proxy for hardware complexity.

• Formula: $BOPs_{layer} = N_w \cdot b_w \cdot b_{in} + N_b \cdot b_b + N_w \cdot b_{acc}$
• This metric accounts for the specific bit-widths of weights, inputs, and accumulators, providing a more accurate estimate of FPGA resource usage (LUTs, FFs, DSPs).

3. Key Contributions

• Hardware-Aware Workflow: A systematic procedure for compressing GNNs specifically for L1 triggers, balancing model architecture, quantization, and pruning against FPGA constraints.
• BOPs Metric: Introduction and application of Bit Operations as a primary design metric to predict FPGA feasibility before full synthesis.
• End-to-End Validation: The paper bridges the gap between offline model training and online FPGA implementation, validating the design on real Belle II collision data and out-of-context FPGA synthesis.

4. Results

Performance Metrics (Physics)

Evaluated on Belle II 2024 collision data (approx. 2.5 million CDC hits):

• Full-Precision Baseline: AUC = 0.974, Background Rejection = 94.2% (at 95% hit efficiency).
• Final Compressed Model (Pruned + Quantized): AUC = 0.968, Background Rejection = 90.9%.
• Conclusion: The cumulative degradation in performance is modest (AUC drop of only 0.006), preserving near-baseline physics performance.

Hardware Metrics (Complexity)

• BOPs Reduction: The computational cost was reduced from 116.6 MBOPs (full-precision) to 1.8 MBOPs (final configuration).
• Improvement Factor: A reduction of more than two orders of magnitude (~65x).
• Target Compliance: The final 1.8 MBOPs falls within the target range of 1.0–2.5 MBOPs per sector.

FPGA Implementation (Out-of-Context)

Validated on an AMD Ultrascale XCVU190:

• Latency: 632.4 ns (at 128 MHz), satisfying the sub-microsecond requirement.
• Resource Utilization:
  • Look-Up Tables (LUTs): 35.65%
  • Flip-Flops (FFs): 29.75%
  • DSPs: 0% (Crucial for cost and power efficiency).
• Graph Size Tested: 495 nodes, 2163 edges (representative of a sector).

5. Significance

This work demonstrates that Graph Neural Networks can be successfully deployed in the most restrictive environments of high-energy physics experiments (L1 triggers) through rigorous hardware-aware design.

• Feasibility: It proves that complex pattern recognition tasks can be offloaded to FPGAs without requiring massive DSP resources, relying instead on efficient logic utilization (LUTs/FFs).
• Scalability: The methodology allows the Belle II trigger system to handle increasing background rates at high luminosity while maintaining high signal efficiency.
• Generalizability: The workflow (quantization-aware training + pruning + BOPs metric) provides a template for deploying other AI models in latency-critical, resource-constrained hardware systems beyond particle physics.