A Fully Open-source Implementation of an Analog 8-PAM Demapper for High-speed Communications

This paper presents a fully open-source design and simulation of an energy-efficient analog 8-PAM demapper implemented in IHP SG13G2 SiGe BiCMOS technology using MOSFETs, achieving 0.33 pJ/bit at 1 Gbit/s.

The Gist

Imagine you are trying to send a secret message to a friend across a noisy room. In the modern world, we don't just shout "Yes" or "No"; we use complex codes where different volumes and tones represent different letters. This is how high-speed internet works: it packs a lot of data into a single signal.

However, there's a problem. When your friend (the receiver) hears the signal, it's often fuzzy because of the background noise. To decode the message, they usually have to:

1. Listen to the fuzzy sound.
2. Stop and think (convert the sound into digital numbers).
3. Do complex math on a computer chip to guess what the original message was.

This "stop and think" process (using digital computers) is slow and eats up a lot of battery power. As our internet speeds get faster, these digital chips are getting too hot and using too much energy.

The Big Idea: "Thinking" While Listening

The authors of this paper asked a simple question: What if the receiver could guess the message while it's still a sound wave, without ever turning it into digital numbers first?

They built a tiny, analog "translator" (called a Demapper) that works like a human ear trying to guess words in a noisy room, but done with microscopic electronic parts.

The Recipe: 8 Flavors of Ice Cream

To make this concrete, imagine the signal isn't just "loud" or "soft." Imagine it's an ice cream machine that can dispense 8 different flavors (from very mild to very strong).

• In a digital system, the machine would taste the ice cream, write down "Flavor #5," and then a computer would calculate the message.
• In this new Analog system, the machine has a special set of levers. Depending on how strong the flavor is, the levers automatically push out a specific "confidence score" (a voltage) that says, "I'm pretty sure this is Flavor #5, but maybe it's #4."

The paper focuses on a system with 8 levels (8-PAM), which is like having 8 distinct steps on a ladder.

The Two Competitors: The Heavyweight vs. The Sprinter

The researchers tried two different ways to build this analog translator:

1. The "BJT" Design (The Old School Heavyweight):

   • This uses older technology (like a heavy, reliable weightlifter).
   • Pros: It's very accurate. It guesses the flavor correctly almost every time.
   • Cons: It's slow. When the flavor changes quickly, this weightlifter gets "stuck" for a moment (a technical issue called saturation) before it can lift the next weight. It's like a heavy truck taking a long time to stop and start again.

2. The "MOSFET" Design (The New Sprinter):

   • This uses modern, lighter technology (like a sprinter).
   • Pros: It is incredibly fast. It can switch flavors instantly without getting stuck. It uses very little energy.
   • Cons: It's slightly less accurate than the heavyweight. It might guess "Flavor #4" when it's actually "Flavor #5" a tiny bit more often.

The Surprise: Even though the Sprinter (MOSFET) is slightly less accurate at guessing, it is so much faster and efficient that it wins the race for high-speed internet. It can handle 1 billion bits of data per second while using almost no energy (0.33 pJ/bit). That's like running a marathon while sipping a single drop of water.

Why This Matters: The "Open Source" Revolution

Perhaps the most exciting part of this paper isn't just the speed, but how they built it.

• Usually, designing these tiny chips is like trying to build a car using a secret, expensive blueprint that only a few big companies own.
• The authors used fully open-source tools. They used free software and public blueprints (like a "Linux for chips") to design and simulate this circuit.
• The Analogy: Imagine if anyone could design a Ferrari engine using free software and open blueprints, and then prove it works just as well as the expensive ones. This democratizes technology, allowing universities and small startups to innovate without needing millions of dollars in licenses.

The Bottom Line

This paper is a proof-of-concept showing that we can build super-fast, ultra-low-power internet receivers that skip the slow "digital thinking" step. By using a clever analog design (the Sprinter) and open-source tools, they've shown a path toward faster, greener communication systems that don't overheat our devices.

In short: They taught the receiver to "guess while listening" using a fast, lightweight, and free-to-build design, paving the way for the next generation of super-fast internet.

Technical Summary

Here is a detailed technical summary of the paper "A Fully Open-source Implementation of an Analog 8-PAM Demapper for High-speed Communications."

1. Problem Statement

Modern high-speed communication systems rely on spectrally efficient modulation formats (e.g., QAM) combined with Forward Error Correction (FEC). In conventional receivers, an Analog-to-Digital Converter (ADC) is required to convert the received analog signal into digital data before computing Log-Likelihood Ratios (LLRs) for the FEC decoder.

• The Bottleneck: As data rates increase, the power consumption of digital circuits (specifically ADCs and digital demappers) grows rapidly, making it difficult to maintain low energy-per-bit.
• The Gap: While analog FEC decoders have been researched, analog demappers (which compute LLRs directly in the analog domain) are rarely studied. Existing literature (e.g., [11], [12]) is limited to 4-PAM, often uses hybrid BJT/MOSFET designs, lacks performance metrics (speed/energy), and does not utilize open-source design flows.

2. Methodology

The authors propose a fully analog 8-PAM demapper designed to replace the digital demapper in a receiver chain, generating soft information (LLRs) directly from the analog input voltage.

• System Model:

  • Modulation: 8-Pulse Amplitude Modulation (8-PAM), equivalent to 64-QAM in terms of bit mapping, using Gray coding.
  • LLR Calculation: The design targets the max-log approximation of the LLR, which converts the non-linear relationship between the received signal and LLRs into a piece-wise linear function.
  • Architecture: A cell-based approach where individual circuit cells generate specific segments of the piece-wise linear function. These cells are combined (summed/subtracted) to form the final LLR outputs for the three bits ($b_1, b_2, b_3$).

• Circuit Design Evolution:

  • Baseline (BJT Design): The authors revisit a design from [11] which uses a hybrid approach: PMOS differential pairs driving BJT current mirrors. While linear, BJTs suffer from charge storage effects when entering saturation, limiting speed.
  • Proposed (MOSFET Design): The authors propose a fully MOSFET-based implementation. They replace the BJTs in the current mirrors with NMOS transistors.
    • Trade-off: This slightly reduces linearity (specifically for the 3rd bit) but eliminates the saturation delay associated with BJTs.
  • Technology: Implemented using the IHP SG13G2 SiGe BiCMOS process via the IHP-Open-PDK. This process integrates high-speed HBTs with a functional CMOS platform.

• Simulation Environment:

  • The entire design and simulation flow relies on open-source tools (Qucs-S, ngspice, OpenVAF).
  • Input/Output mapping is handled via scaling factors ($\alpha, \beta, \gamma_k, \zeta_k$) to map the constellation points to the circuit's voltage range and minimize squared amplitude error against theoretical LLRs.

3. Key Contributions

1. First Open-Source 8-PAM Analog Demapper: This is the first fully open-source implementation of an analog demapper for 8-PAM (extending previous 4-PAM work).
2. Fully MOSFET Architecture: The paper introduces a fully MOSFET-based design that improves upon the hybrid BJT/MOSFET approach found in literature, prioritizing speed and power efficiency over perfect linearity.
3. Comprehensive Performance Analysis: Unlike prior works, this paper provides detailed metrics on Bit Error Rate (BER), Generalized Mutual Information (GMI), settling time, and energy efficiency.
4. Open-Source EDA Validation: The work demonstrates the viability of using open-source Process Design Kits (PDKs) and Electronic Design Automation (EDA) tools for high-performance analog IC design.

4. Results

• Accuracy (LLR Approximation):

  • The analog outputs closely follow the theoretical "exact" and "max-log" digital references for bit positions $k=1$ and $k=2$.
  • For $k=3$, the MOSFET design deviates more than the BJT design, resulting in a small penalty in Generalized Mutual Information (GMI).
  • Rate Penalty: The MOSFET demapper stays within a 3% GMI penalty for SNRs above 3 dB. Interestingly, in the range of -1 dB to 9 dB SNR, the analog demappers actually outperform the digital max-log approximation because they approximate the exact LLRs better for the most significant bits.

• Speed and Dynamic Response:

  • Settling Time: The MOSFET design settles significantly faster ($\approx 2$ ns) than the BJT design.
  • Cause: The BJT design exhibits a "plateau" in voltage transitions when transistors exit saturation (due to base charge discharge). The MOSFET design avoids this saturation region entirely, allowing for faster switching.
  • Symbol Rate: The MOSFET design maintains a constant, near-ideal BER up to 350 Msamples/s (equivalent to 1 Gbit/s for 8-PAM). The BJT design shows increasing BER as the symbol rate rises due to settling delays.

• Energy Efficiency:

  • The MOSFET design consumes 0.35 mW at 1 Gbit/s.
  • This translates to an energy efficiency of 0.33 pJ/bit.
  • The BJT design required a much higher bias current (100 µA vs. 10 µA per cell for MOSFET) to achieve comparable BER, making it less energy-efficient.

5. Significance

• Energy Efficiency: The design demonstrates that analog demapping can achieve extremely low energy consumption (0.33 pJ/bit), addressing the power bottleneck of high-speed digital receivers.
• High-Speed Viability: By eliminating the saturation delay of BJTs, the fully MOSFET approach proves that analog demappers can operate at Gbit/s speeds, making them viable candidates for future high-throughput communication systems.
• Open-Source Ecosystem: The successful implementation using IHP-Open-PDK and open-source tools validates the maturity of the open-source hardware design ecosystem, lowering the barrier to entry for advanced IC research.
• Future Outlook: The paper establishes a foundation for future research into analog demappers for denser constellations (e.g., geometrically shaped QAM) and analog FEC decoders, moving toward fully analog receiver chains.