Design Conductor: An agent autonomously builds a 1.5 GHz Linux-capable RISC-V CPU

The paper introduces Design Conductor, an autonomous agent that leverages frontier models to independently design, verify, and generate a tape-out ready 1.48 GHz RISC-V CPU (VerCore) from a text specification to GDSII layout in just 12 hours, marking the first instance of an agent building a complete, working CPU end-to-end.

The Gist

Imagine you want to build a custom, high-performance car engine from scratch. Usually, this process takes a team of 100 expert engineers, costs hundreds of millions of dollars, and takes three years. They have to design the blueprint, build the prototype, test it thousands of times, and fix any tiny leaks or cracks before they can even think about mass-producing it.

Now, imagine a super-intelligent robot architect named Design Conductor (DC).

This paper describes how the "Verkor Team" taught this robot to do the entire job of building a computer chip (specifically a RISC-V CPU called "VerCore") all by itself, in just 12 hours.

Here is the breakdown of how they did it, using simple analogies:

1. The Challenge: The "Impossible" Job

Building a chip is like trying to write a novel, translate it into a foreign language, build a physical book, and print it, all while ensuring there are zero typos.

• The Cost: If you make one mistake in the final design, the whole batch of chips is useless. Since printing a chip costs millions, you can't just "fix it later."
• The Time: It usually takes years of human labor to get it right.

2. The Solution: The Autonomous Conductor

Design Conductor isn't just a chatbot that writes code. It's an autonomous agent that acts like a project manager, an engineer, a tester, and a construction worker all rolled into one.

• The Input: The humans gave the robot a very simple "recipe" (a 219-word document). It said: "Build a brain for a computer that can do math, run at 1.5 billion cycles per second, and fit in a tiny space."
• The Output: In 12 hours, the robot produced a complete, working design ready to be printed on silicon.

3. How the Robot "Thought" (The Process)

The robot didn't just guess. It followed a strict, disciplined workflow, much like a master chef cooking a complex meal:

• Step 1: The Blueprint (Design Planning):
  The robot read the recipe and wrote a detailed plan. It decided how to arrange the "rooms" (pipeline stages) in the CPU. It even wrote a "living document" that it updated as it found problems.

  • Analogy: Imagine an architect drawing a house, then realizing the stairs are too steep, and immediately redrawing them before laying a single brick.

• Step 2: Building the Rooms (Module Implementation):
  The robot built the CPU piece by piece (the math unit, the memory unit, etc.). For every piece, it built a "test kitchen" (a testbench) to make sure that specific part worked perfectly before moving on.

• Step 3: The Taste Test (Verification & Debugging):
  This is the most critical part. The robot ran its design against a "Gold Standard" simulator (called Spike).

  • The Analogy: Imagine the robot is baking a cake. It compares its cake to a perfect photo of the cake. If the cake is slightly too brown, the robot doesn't just say "close enough." It opens the oven, looks at the batter, checks the temperature logs, and figures out exactly why it burned.
  • The "Aha!" Moment: The paper mentions the robot found a bug where the CPU was forgetting to stop instructions when it jumped to a new task. The robot analyzed the data, realized the "stop signal" was broken, fixed the code, and re-tested. It did this automatically, without human help.

• Step 4: The Final Polish (Timing & Optimization):
  The robot wanted the chip to run at 1.6 GHz. It hit 1.48 GHz. To get there, it had to rearrange the internal wiring to make the "traffic" flow faster.

  • The Discovery: The robot independently figured out a clever way to handle math (using a "Booth-Wallace multiplier") that human experts usually have to teach. It essentially "re-invented the wheel" to make it faster.

4. The Results: A 2011-Level Computer in 12 Hours

The final chip, VerCore, is incredibly fast.

• Speed: It runs at 1.48 GHz.
• Comparison: This is roughly as powerful as an Intel Celeron laptop processor from 2011.
• Significance: In 2011, a team of humans took years to build that. This robot did it in half a day.

5. What the Robot Still Needs Help With

The paper is honest: The robot isn't perfect yet.

• The "Vibe Check": Sometimes the robot makes choices that work but aren't the best choices. It might build a bridge that is strong but uses too much steel. It needs a human "Senior Architect" to look over its shoulder and say, "Hey, you can make this more efficient."
• The "Event" Confusion: Computer chips work differently than regular software. Sometimes the robot gets confused about how signals move in time, treating them like a to-do list instead of a synchronized dance. It eventually figures it out, but it wastes time guessing.

6. The Future: The "Design Factory"

The authors imagine a future where:

• Teams get smaller, but output gets huge. Instead of 100 engineers working on one chip for 3 years, a team of 10 could use robots to design 50 different chips in 3 months.
• Custom Chips for Everyone: Because it's so cheap and fast, companies could make custom chips for niche products (like a specific sensor for a smart fridge) that were previously too expensive to build.
• Human Role Change: Humans stop being "tool jockeys" (people who click buttons in complex software) and become "conductors" (people who set the vision and goals).

Summary

Design Conductor is a proof-of-concept that shows AI can now handle the entire lifecycle of building a computer chip—from a simple text prompt to a finished, physical blueprint. It's like handing a master builder a napkin sketch and having them return with a fully engineered, code-compliant skyscraper in the time it takes to brew a cup of coffee. While it still needs a human supervisor to ensure it's making the smartest choices, it has proven that the era of "AI-built chips" has officially begun.

Technical Summary

Here is a detailed technical summary of the paper "Design Conductor: An agent autonomously builds a 1.5 GHz Linux-capable RISC-V CPU."

1. Problem Statement

The semiconductor industry faces significant barriers to entry due to the extreme cost, time, and complexity of chip design.

• Cost & Time: Bringing a leading-edge chip to market typically costs over $400 million and takes 18–36 months, requiring teams of hundreds.
• Verification Burden: Functional verification consumes over 50% of the total budget to ensure high test coverage, as tape-out errors are financially catastrophic.
• Complexity: The design flow involves interlocking constraints (Power, Performance, Area - PPA) and requires deep expertise in RTL implementation, synthesis, place-and-route (P&R), and timing closure.
• The Gap: Current AI agents often fail to address the entire design flow end-to-end, stopping short of physical implementation (GDSII) or requiring heavy human intervention for timing closure and bug fixing.

2. Methodology: Design Conductor (DC)

The authors introduce Design Conductor (DC), an autonomous agent capable of taking a natural language requirements document and producing a verified, tape-out-ready GDSII layout.

Architecture & Capabilities

DC is built on a scalable, cloud-based infrastructure with the following core capabilities:

• Stable Long-horizon Execution: Manages tasks spanning billions of tokens, maintaining context across architecture definition, RTL coding, and backend physical design.
• Context Management: Dynamically manages LLM context windows, utilizing a dedicated memory system to store design specifications, legacy code analysis, and intermediate results.
• Subagent Orchestration: A "Core" module coordinates specialized subagents for specific tasks:
  • Design Planning: Generates micro-architecture proposals.
  • Module Implementation: Writes RTL and per-module testbenches.
  • System Integration: Integrates modules and runs end-to-end tests.
  • Root Cause Analysis: Debugs functional failures using VCD (Value Change Dump) trace analysis.
  • PPA Closure: Optimizes timing, area, and power via backend tool interaction.
• Verification-Driven Loop: DC does not rely on "vibe coding." It uses a rigorous loop: Generate RTL $\rightarrow$ Simulate against Spike (ISA simulator) $\rightarrow$ Analyze VCD traces $\rightarrow$ Debug $\rightarrow$ Iterate.

The Workflow

1. Input: A 219-word requirements document specifying a RISC-V CPU (RV32I + ZMMUL), 5-stage pipeline, 1.6 GHz target, and ASAP7nm PDK.
2. Design Proposal: DC generates a detailed micro-architecture proposal (including pipeline stages, hazard handling, and multiplier logic) and reviews it "painstakingly" for corner cases.
3. Implementation & Verification:
   • DC writes RTL modules and testbenches.
   • It uses Spike (RISC-V ISA simulator) to generate expected cycle-by-cycle behavior.
   • It compares DUT (Device Under Test) output against Spike.
   • Debugging: When mismatches occur, DC converts VCD traces to CSV, uses Python/Pandas to analyze register writes, identifies root causes (e.g., pipeline flush failures), and patches the RTL.
4. PPA Closure: After functional verification, DC runs synthesis and Place & Route (using OpenROAD). It analyzes timing reports and autonomously modifies RTL (e.g., optimizing forwarding logic or multiplier structures) to meet timing constraints.

3. Key Contributions

• First End-to-End Autonomous CPU: This is the first reported instance of an autonomous agent building a complete, working CPU from a text specification to a verified GDSII layout without human coding intervention.
• Self-Correction Mechanism: The system demonstrated the ability to identify complex bugs (e.g., pipeline flush logic errors during branch jumps) by analyzing simulation traces and autonomously fixing the RTL.
• Architectural Innovation: DC independently discovered and implemented advanced optimizations not explicitly requested in the prompt, including:
  • Early Branch Resolution: Resolving branches in the ID stage.
  • Booth-Wallace Multiplier: Implementing a 4-stage, balanced parallel multiplier.
  • 1-Cycle Branch Penalty: Achieving high performance despite the critical path complexity of a 1-cycle penalty design.
• Scalable Infrastructure: Demonstrated that autonomous agents can manage the massive resource requirements of chip design (hundreds of GBs of VCD data, large DRAM usage for EDA tools).

4. Results

The agent, Design Conductor, built the VerCore CPU in 12 hours.

Metric	Value
Target Frequency	1.6 GHz (Goal)
Achieved Frequency	1.48 GHz (at 7nm ASAP PDK)
Architecture	5-stage In-order, Single-issue, RV32I + ZMMUL
CoreMark Score	3261
Area (ex-cache)	2809 µm²
Historical Context	Comparable to an Intel Celeron SU2300 (2011, 1.2 GHz)
Output	Verified RTL and Tape-out ready GDSII

Note: The design achieved a CPI $\le$ 1.5 and successfully passed integration tests including MD5 and CoreMark.

5. Significance & Future Outlook

• Paradigm Shift: This work suggests a future where chip design timelines shrink from years to months (3–6 months) and costs drop significantly, enabling "low-volume" custom chips that were previously economically unviable.
• Role of Human Engineers: The authors argue that human architects will transition from "tool-jockeys" (writing RTL, running scripts) to strategic guides. Humans will define high-level objectives and constraints, while DC handles the execution, exploration of design space, and verification.
• Limitations & Lessons Learned:
  • Architectural Reasoning: LLMs sometimes make sub-optimal initial choices (e.g., inefficient forwarding paths) and require timing feedback to correct them.
  • RTL Semantics: Models sometimes treat Verilog (event-driven) like sequential software code, leading to debugging delays, though they eventually self-correct via tool feedback.
  • Specification Rigor: The input prompt must be extremely precise; vague constraints lead to performance degradation.
• Conclusion: Frontier models, when coupled with robust verification loops and infrastructure, can autonomously navigate the complex trade-offs of semiconductor design, potentially democratizing access to custom silicon.