AnalogToBi: Device-Level Analog Circuit Topology Generation via Bipartite Graph and Grammar Guided Decoding

AnalogToBi is a novel framework for automatic device-level analog circuit topology generation that combines bipartite graph representations, grammar-guided decoding, and data augmentation to achieve high validity and novelty while ensuring electrical correctness without human intervention.

The Gist

Imagine you are trying to teach a robot to design a complex machine, like a car engine or a sophisticated audio amplifier. In the world of electronics, these machines are called analog circuits.

For decades, designing these circuits has been like trying to build a house by guessing where the bricks go. You need a human expert to know exactly how to arrange the transistors (the tiny switches inside the chip) so the electricity flows correctly. If you get the arrangement wrong, the circuit is "broken" (electrically invalid) and won't work at all.

This paper introduces AnalogToBi, a new AI system that acts like a master architect who can not only draw blueprints but also invent entirely new, working designs from scratch.

Here is how it works, broken down into simple analogies:

1. The Problem: The Robot's "Bad Habits"

Previous AI attempts to design circuits were like a student who memorized the answers to a math test but didn't understand the math.

• The Issue: If you asked the old AI to design a specific type of amplifier, it would just copy-paste a design it had seen before. It couldn't invent anything new.
• The Result: It often produced "broken" circuits (like a house with a door leading to a wall) or just repeated the same old designs over and over.

2. The Solution: The "AnalogToBi" Framework

The authors built a smarter system using four clever tricks. Think of it as giving the robot a new set of tools and rules.

A. The "Order Card" (Circuit Type Token)

Imagine you walk into a restaurant. In the past, the chef just started cooking whatever they felt like.

• The Fix: Now, you hand the chef an Order Card that says, "I want a Pizza" or "I want a Salad."
• In the Paper: The user tells the AI exactly what the circuit needs to do (e.g., "Make an Amplifier" or "Make a Comparator"). This gives the AI a clear goal to aim for, rather than guessing.

B. The "Two-Column Ledger" (Bipartite Graph)

This is the most important innovation.

• The Old Way: Imagine trying to describe a city by listing every single street address in a long, confusing line. If you say "House A is next to House B," and then "House B is next to House C," it gets messy. The AI would just memorize the order of the houses rather than understanding the city layout.
• The New Way (AnalogToBi): Imagine a Two-Column Ledger.
  • Column 1: The Buildings (The electronic components like transistors).
  • Column 2: The Roads (The wires connecting them).
  • The AI doesn't just list them; it draws lines between the buildings and the roads. This separates what the part is from where it is. It forces the AI to think about the structure (how things connect) rather than just memorizing a list of names.

C. The "Grammar Police" (Grammar-Guided Decoding)

Even with a good blueprint, a robot might make a silly mistake, like connecting a wire to nothing (a "floating" wire) or creating a short circuit.

• The Fix: The AI has a built-in Grammar Police officer.
• How it works: As the AI tries to draw the circuit, the officer checks every move.
  • AI tries to draw a wire: "Okay, that's allowed."
  • AI tries to connect a wire to thin air: "STOP! That's illegal grammar. You must connect it to a building first."
• The Result: The AI is physically prevented from drawing broken circuits. It only outputs designs that are electrically valid.

D. The "Name Game" (Device Renaming)

This is a trick to stop the AI from cheating by memorizing.

• The Problem: If the AI sees a circuit with a transistor named "Bob," it might think "Bob" is the secret to success. If it sees "Bob" again, it copies the whole thing.
• The Fix: The training data is shuffled. The AI is shown the exact same circuit, but "Bob" is now called "Charlie," and "Charlie" is called "Dave."
• The Result: The AI realizes that the name doesn't matter; only the connection matters. It learns the principles of how to build a circuit, not just the specific names of the parts. This makes it much better at inventing new designs.

3. The Results: A New Era of Design

When the researchers tested AnalogToBi:

• 97.8% Validity: Almost every circuit it drew was a working, legal circuit. (Previous methods often failed here).
• 92.1% Novelty: It didn't just copy old designs; it invented 9 out of 10 new structures that had never been seen before.
• Real-World Test: They took the AI's designs, built them in a computer simulation (SPICE), and ran them. The AI-designed circuits performed better than those made by other AI methods, and they were competitive with designs made by human experts.

The Big Picture

AnalogToBi is like teaching a robot to be a creative engineer rather than a photocopier. By using a smart way to organize information (the ledger), strict rules to prevent mistakes (the grammar police), and a trick to stop memorization (the name game), it can now automatically invent high-quality, working electronic circuits without needing a human to hold its hand.

This is a huge step forward because it could eventually allow us to design complex chips faster, cheaper, and with more innovation than ever before.

Technical Summary

Here is a detailed technical summary of the paper "AnalogToBi: Device-Level Analog Circuit Topology Generation via Bipartite Graph and Grammar Guided Decoding."

1. Problem Statement

The design of analog circuits remains heavily dependent on expert human knowledge, particularly in the topology generation phase (determining the structural arrangement of devices). While recent transformer-based approaches (e.g., Large Language Models) have shown promise, they face three critical limitations:

• Limited Functional Controllability: Existing models struggle to generate specific circuit types (e.g., an OpAmp vs. a Comparator) on demand.
• Memorization vs. Generalization: Models often memorize training data patterns rather than learning underlying structural principles, leading to a lack of novelty.
• Electrical Invalidity: Generated circuits frequently contain structural errors (e.g., floating nodes, short circuits) that make them non-functional or impossible to simulate.

Current methods either rely on predefined topologies (search-based), refine existing designs (refinement-based), or generate behavior-level blocks (lacking device-level flexibility). There is a need for a framework that generates device-level topologies from scratch with explicit functional control, high validity, and high novelty.

2. Methodology: AnalogToBi Framework

The authors propose AnalogToBi, a generative framework built on a compact, decoder-only Transformer model (11.3M parameters). The framework integrates four key innovations:

A. Circuit-Type Token for Functional Control

Unlike previous methods that start generation from a fixed reference token (e.g., $V_{SS}$), AnalogToBi accepts a Circuit-Type Token (e.g., CIRCUIT OpAmp, CIRCUIT Comparator) as a user input. This token conditions the generation process, allowing explicit control over the target functionality.

• Challenge: Simply adding type tokens to existing models causes severe memorization (novelty drops from 68% to 45% in baselines).
• Solution: This is mitigated by the novel circuit representation and data augmentation strategies described below.

B. Bipartite Graph Circuit Representation

To decouple structural relationships from token identities and reduce memorization, AnalogToBi abandons the conventional "device-pin" representation (where every pin is a unique token like NM1S, NM1G). Instead, it uses a Bipartite Graph representation:

• Nodes: Two distinct sets: Device Nodes (e.g., NM1, PM1) and Net Nodes (e.g., VDD, NET1).
• Edges: Represent pin connections. Pin semantics (Source, Gate, Drain, Body) are encoded as typed edges rather than unique tokens.
• Benefit: This representation treats pins as relational attributes rather than fixed positions, forcing the model to learn structural logic (how devices connect to nets) rather than memorizing specific token sequences.

C. Grammar-Guided Decoding

To ensure electrical validity without relying on massive datasets, the authors implement a Grammar-Guided Decoding strategy using a state machine.

• State Machine: The generation process is modeled as a sequence of states defined by the token categories (Circuit Type, Device, Net, Edge/Pin).
• Constraints: The grammar strictly masks invalid transitions. For example, if a Device token is generated, the next token must be a Pin/Edge token; if a Pin token is generated, the next must be a Net token.
• Termination: Generation only terminates when all device pins are connected and no internal nets are floating, guaranteeing electrical completeness.

D. Device Renaming Data Augmentation

To further combat memorization, the authors introduce a data augmentation strategy where device identifiers (e.g., NM1) are randomly renamed (e.g., to NM7) while preserving the circuit's topology and electrical equivalence.

• Synergy: This augmentation is highly effective only when combined with the Bipartite Graph representation. In device-pin representations, renaming breaks the rigid positional patterns, causing validity to collapse. In the bipartite representation, it forces the model to learn invariant structural patterns.

3. Key Contributions

1. Explicit Functional Control: The first device-level generator that allows users to specify the circuit type (e.g., OpAmp, LDO) via a token, achieving high classification accuracy (91.3% average).
2. Novel Representation: Introduction of a bipartite graph representation that separates devices and nets, effectively decoupling structural reasoning from token memorization.
3. Grammar-Guided Validity: A state-machine-based decoding mechanism that enforces electrical rules during generation, eliminating the need for post-hoc filtering or human-in-the-loop reinforcement learning.
4. Fully Automated Training: The framework trains from scratch without human expert feedback (HITL), relying solely on the dataset and the proposed augmentation/grammar strategies.

4. Experimental Results

The model was trained on a dataset of 2,165 SPICE netlists (expanded to ~397k sequences via augmentation) and evaluated against state-of-the-art baselines (AnalogCoder, LaMAGIC, AnalogGenie).

• Validity: Achieved 97.8% (generated circuits are electrically valid and can be converted to SPICE netlists). This outperforms AnalogGenie (58.2% without HITL) and is comparable to refinement-based methods.
• Novelty: Achieved 92.1% (generated topologies are not isomorphic to training data).
• Valid & Novel: 89.9% of generated circuits are both valid and novel.
• Memorization: The 10-gram matching rate (a proxy for memorization) dropped to 0.0% with the full framework, compared to 59.7% for baseline device-pin representations.
• Performance (SPICE Simulation):
  • Generated OpAmps achieved a Figure of Merit (FoM) of 168.5 MHz·pF/mW, significantly outperforming AnalogCoder (1.7) and AnalogGenie (36.5).
  • Generated Comparators demonstrated correct rail-to-rail switching behavior in transient simulations.
  • These results were achieved using simple rule-based sizing, without computationally expensive optimization loops.

5. Significance

AnalogToBi represents a significant leap toward fully automated analog circuit design. By solving the "validity vs. novelty" trade-off through structural representation and grammar constraints, it enables the generation of diverse, high-quality, and functional circuit topologies without human intervention.

• Practical Impact: It reduces the reliance on scarce expert knowledge for the initial topology phase, allowing for rapid prototyping and exploration of the design space.
• Scalability: The approach is scalable to various circuit types and does not require expensive reinforcement learning loops with human feedback.
• Future Direction: The work establishes a foundation for integrating topology generation directly into Electronic Design Automation (EDA) flows, potentially accelerating the development of next-generation analog and mixed-signal systems.