Predictive first-principles simulations for co-designing next-generation energy-efficient AI systems

This Perspectives article argues that predictive, first-principles simulations spanning materials to architectures are essential for co-designing specialized hardware capable of achieving orders-of-magnitude improvements in the energy efficiency of next-generation AI systems.

The Gist

Here is an explanation of the paper, translated into everyday language with some creative analogies.

The Big Problem: AI is Getting Thirsty

Imagine Artificial Intelligence (AI) as a giant, super-smart brain that is constantly learning and thinking. Right now, this brain is getting incredibly "thirsty" for electricity. As AI gets smarter, the data centers powering it are consuming so much energy that it's becoming unsustainable. It's like trying to power a city with a single lemon battery; eventually, you run out of juice.

The paper argues that we can't just build bigger power plants to solve this. Instead, we need to make the AI brain itself much more efficient.

The Bottleneck: The "Matrix Multiplication" Traffic Jam

In modern AI (like the chatbots you use), the most energy-hungry task is a specific math operation called Matrix Multiplication.

• The Analogy: Imagine a massive library where you have to cross-reference millions of books to find a single answer. In a standard computer, this is like a librarian running back and forth between shelves, carrying heavy boxes of books. It takes a lot of time and energy.
• The Reality: In AI, these "boxes" are data, and the "running" is moving electricity through wires. The paper says that 90% of the energy is wasted just moving these numbers around, not actually doing the math.

The Proposed Solution: "Beyond-Digital" Hardware

Currently, almost all computers use Digital CMOS technology (the standard silicon chips in your phone). The authors say we've squeezed this technology pretty dry. To get a massive leap in efficiency (100x or even 1,000x better), we need to invent a new type of hardware. They call this "Beyond-Digital-CMOS."

Think of it this way:

• Digital CMOS is like a light switch: It's either ON or OFF. It's great for logic, but it's inefficient for the specific math AI needs.
• Beyond-Digital is like a dimmer switch or a water valve. It can handle the "flow" of information in a more natural, continuous way, using less energy to do the same job.

The Challenge: Designing from Scratch

Here is the tricky part: We don't fully know what these new "dimmer switches" should look like yet.

• The Old Way: Engineers usually guess a design, build a prototype, test it, and then tweak it. This is slow and expensive.
• The New Way (Co-Design): The authors propose a "Co-Design" approach. This means designing the material, the device, the wires, and the software all at the same time, rather than one by one.

The Secret Weapon: "Crystal Ball" Simulations

How do you design something you haven't built yet? You use Predictive First-Principles Simulations.

• The Metaphor: Imagine you are an architect designing a skyscraper. Instead of building a full-scale model out of steel and glass (which costs millions), you use a super-advanced computer simulation that knows the laws of physics perfectly. You can simulate a hurricane, an earthquake, or a fire, and the computer tells you exactly how the building will react before you lay a single brick.
• In the Paper: The authors use quantum physics simulations (specifically something called NEGF) to act as this crystal ball. They can simulate how electrons move through a tiny wire or a new type of transistor at the atomic level.
  • They can predict: "If we make this wire 5 nanometers wide and use this specific material, how much energy will it leak?"
  • They can predict: "If we change the shape of this transistor, will it switch faster?"

The Workflow: From Atoms to AI

The paper outlines a roadmap (Figure 5 in the text) that connects the tiny world to the big world:

1. The Micro World (Atoms): They simulate individual atoms and electrons to find the perfect material and shape for a new chip.
2. The Mini World (Circuits): They translate those atomic simulations into "compact models" (simplified rules) that circuit designers can use.
3. The Macro World (Systems): They plug those rules into a simulation of the whole AI system to see: "How much energy does it take to generate one word (token)?"
4. The Feedback Loop: If the system is still too energy-hungry, they go back to step 1 and tweak the atomic design.

Why This Matters

The authors argue that without these "crystal ball" simulations, we are just guessing. We might build a new chip that looks great on paper but fails in the real world because of tiny quantum effects or heat issues.

By using these predictive simulations, we can:

1. Reverse Engineer: Start with the goal (e.g., "I need a chip that uses 1/100th the energy") and work backward to find the perfect atomic design.
2. Avoid Dead Ends: Stop wasting money building chips that won't work.
3. Bridge the Gap: Connect the physics of atoms directly to the performance of AI applications.

The Bottom Line

The paper is a call to action for scientists and engineers to stop treating hardware and software as separate things. They need to work together, using advanced physics simulations as a guide, to build a new generation of AI computers that are powerful enough to run our future, but efficient enough not to melt the planet.

In short: We need to stop building AI computers with the same old tools. We need to use quantum physics "crystal balls" to design brand new, super-efficient machines from the atom up.

Technical Summary

Here is a detailed technical summary of the paper "Predictive first-principles simulations for co-designing next-generation energy-efficient AI systems."

1. Problem Statement

The paper addresses the unsustainable growth in energy consumption driven by Artificial Intelligence (AI) workloads, particularly Generative AI (e.g., GPT models).

• The Bottleneck: In modern AI architectures, Matrix-Vector (MatVec) and Matrix-Matrix (MatMul) multiplications dominate both computational cost and energy consumption.
• Limitations of Current Tech: While GPUs and specialized accelerators (TPUs, NPUs) have improved efficiency, they are still bound by digital CMOS limits. Neuromorphic approaches often suffer from low throughput, and digital CMOS scaling is slowing down regarding energy efficiency per operation.
• The Gap: Existing optimization strategies often treat materials, devices, interconnects, and architectures in isolation. There is a lack of a unified framework to identify device operating regimes that can deliver orders-of-magnitude improvements in energy efficiency (targeting 100x–1000x gains) for AI accelerators.
• The Challenge: Designing "Beyond-Digital-CMOS" accelerators (analog, hybrid, or neuromorphic) requires knowing the optimal device characteristics for specific non-digital computational schemes, which are currently unknown.

2. Methodology

The authors propose a predictive, first-principles co-design framework that bridges nanoscale physics with system-level workload metrics without relying on fitting parameters.

• Core Simulation Engine: The methodology utilizes Non-Equilibrium Green's Function (NEGF) formalism within an open-system, charge-self-consistent framework.
  • Physics: It treats electron transport as an open-boundary quantum problem, solving the Schrödinger equation coupled with Poisson electrostatics.
  • Algorithm: It employs the Contact Block Reduction (CBR) method, which scales linearly ($O(N)$) with system size, allowing for efficient simulation of multi-terminal 2D/3D open devices.
  • Key Feature: The simulations are fitting-parameter-free. They use fixed physical parameters (geometry, materials, doping) to predict electrical characteristics (I-V curves, capacitance, resistivity) directly.
• Co-Design Workflow (The "Mini-Roadmap"):
  1. First-Principles Simulation: Predicts device/interconnect properties (e.g., tunneling currents, leakage, contact resistance).
  2. Compact Modeling: Translates quantum transport data into SPICE-compatible compact models (using physics-based, machine learning, or lookup-table approaches).
  3. Circuit & System Simulation: Uses these models to simulate large-scale accelerators under specific workloads (e.g., GPT inference/training).
  4. Feedback Loop: System-level metrics (energy per token, throughput) feed back to optimize material selection, device geometry, and doping profiles (Inverse Design).

3. Key Contributions

The paper makes three primary technical contributions:

1. Validation of Predictive Quantum Transport:

   • Demonstrates that open-system NEGF simulations can accurately predict experimental results for Si:P $\delta$-layer interconnects, capturing size-dependent resistivity and quantum conductance steps.
   • Successfully predicted the conductivity of $\delta$-layer tunnel junctions before experimental validation ("Theory-first" approach).
   • Modeled Gate-All-Around FETs (GAAFETs), accurately identifying leakage paths and non-thermionic behaviors in the deep sub-threshold regime.

2. Establishment of a Multi-Scale Co-Design Framework:

   • Proposes a rigorous pathway connecting atomic-scale physics (doping, interfaces) $\rightarrow$ device physics (leakage, drive current) $\rightarrow$ circuit metrics (delay, energy) $\rightarrow$ system metrics (tokens/sec, energy/token).
   • Highlights that optimizing devices in isolation is insufficient; interconnect parasitics (RC delay) and data movement costs must be co-optimized with active devices.

3. Definition of "Beyond-Digital-CMOS" Requirements:

   • Argues that future AI accelerators need not be strictly neuromorphic but must be "Beyond-Digital-CMOS" to break current efficiency ceilings.
   • Identifies that for analog/hybrid schemes, the definition of a "good transistor" shifts from high on/off ratios (digital) to signal amplification quality and linear regime fidelity.

4. Key Results & Findings

• Interconnects: Simulations of Si:P $\delta$-layer interconnects revealed that as dimensions shrink, quantum confinement leads to size-dependent resistivity and quantized spatial distributions of current-carrying modes. These effects significantly impact contact resistance and must be accounted for in compact models.
• Tunnel Junctions: The framework successfully predicted tunneling resistances in $\delta$-layer junctions, showing that quantum transport treatment is essential for ultra-low-energy compute fabrics.
• GAAFETs: The models identified that drain-induced dielectric barrier lowering and new tunneling paths are dominant leakage mechanisms in advanced nodes, justifying the need for open-boundary quantum treatments over semiclassical models.
• System Impact: The paper demonstrates that without accurate, physics-based compact models derived from first principles, system-level estimates for energy and throughput are unreliable. Specifically, interconnect losses can dominate system energy, negating device-level improvements if not co-designed.

5. Significance

• Accelerating Hardware Discovery: By enabling "inverse design," this framework allows researchers to determine the optimal material and device geometry to minimize energy per Multiply-Accumulate (MAC) operation before fabrication, reducing the trial-and-error cycle.
• Bridging the Gap: It provides the missing link between theoretical device physics and practical AI workload performance, ensuring that novel device concepts are evaluated against real-world constraints (variability, leakage, interconnects).
• Policy & Roadmap Alignment: The work supports national roadmaps (e.g., U.S. DOE AMMTO) aiming for 100x–1000x energy efficiency improvements in microelectronics by providing a scientifically rigorous method to achieve these targets.
• Future-Proofing AI: As AI models grow larger, the energy cost of training and inference becomes a critical barrier. This co-design approach is presented as a necessary evolution to sustain the growth of generative AI without an unsustainable increase in power consumption.

In summary, the paper argues that predictive, first-principles simulations are the critical enabler for the next generation of AI hardware, moving beyond empirical scaling to a physics-driven, co-designed approach that integrates materials, devices, and architectures to achieve massive energy efficiency gains.