In-Situ Timing Diagnosis of PDN and Configuration-Upset-Induced Routing Delay Degradation in SRAM-based FPGAs

This paper presents a scalable, non-intrusive in-situ timing diagnosis architecture for SRAM-based FPGAs that utilizes distributed phase-swept delay monitoring to probabilistically characterize and spatially differentiate between global power-distribution-network degradation and localized configuration-induced routing perturbations during normal operation.

The Gist

Imagine you have a massive, incredibly complex city made entirely of roads and traffic lights. This city is an FPGA (a type of computer chip that can be reprogrammed to do different jobs). The "roads" are the wires that carry data, and the "traffic lights" are the switches that direct that data.

Usually, when engineers design a city, they use a map to predict how long it takes a car to get from Point A to Point B. They assume the roads are perfect and the weather is always sunny. But in the real world, things go wrong. Sometimes, the whole city's power grid gets a little shaky (like a brownout), slowing down every car at once. Other times, a specific traffic light gets stuck or a new, confusing detour is accidentally built on just one street, causing a massive jam in that specific neighborhood.

The Problem:
Until now, engineers had a very blunt tool for checking traffic. It was like a security guard who only shouted "STOP!" when a car crashed. They knew something was wrong, but they didn't know what was wrong. Was it a city-wide power issue? Or just a broken light on one street? Without knowing the cause, they couldn't fix it properly.

The Solution (The Paper's Big Idea):
This paper introduces a new, super-smart traffic monitoring system that lives inside the city itself. It doesn't stop the cars; it just watches them while they drive.

Here is how it works, broken down with simple analogies:

1. The "Invisible Eavesdroppers" (Delay Taps)

Imagine placing tiny, invisible microphones at every major intersection in the city. These are called Delay Taps.

• How they work: They listen to the cars (data signals) as they pass by.
• The trick: They are designed so perfectly that they don't slow the cars down or change the traffic flow. They are like a ghost listening in; the cars don't even know they are there.

2. The "Slow-Motion Camera" (Phase-Swept Sampling)

Instead of just taking a snapshot, these microphones take thousands of photos of the same car passing an intersection, but they shift the timing of the camera slightly for every single photo.

• The result: They build a "probability map." Instead of saying "The car took 5 seconds," they say, "90% of the time, the car arrives in 5 seconds, but sometimes it's 5.1 seconds, and rarely 4.9 seconds."
• Why this matters: This gives them a detailed picture of the variability and uncertainty of the traffic, not just a single number.

3. The "Detective" (Diagnosis Architecture)

All these microphones send their data to a central detective (the Diagnosis Controller). The detective looks at the patterns across the whole city to figure out what's happening.

The detective can now spot two very different types of problems:

• Scenario A: The "Brownout" (PDN Stress)

  • What happens: The city's power supply dips slightly.
  • The Signature: The detective sees that every single car in the entire city is slowing down by the exact same amount. The traffic is uniformly slower, but the variability (how much some cars are faster or slower than others) stays the same.
  • The Fix: The detective knows, "Ah, the whole grid is weak. We need to boost the power or slow down the city's clock speed globally."

• Scenario B: The "Bad Detour" (Routing Perturbation)

  • What happens: A configuration error (like a bit-flip in memory) accidentally adds a weird, extra loop to a specific street.
  • The Signature: The detective sees that cars on one specific street are taking much longer, and their arrival times are all over the place (some are super late, some are on time). Meanwhile, the rest of the city is driving normally.
  • The Fix: The detective knows, "This isn't a power issue. There's a specific broken road. We need to re-route traffic or fix that specific intersection."

Why This is a Big Deal

Before this, engineers were like doctors trying to diagnose a patient by only checking if they had a fever. They knew the patient was sick, but they didn't know if it was the flu (global issue) or a broken leg (local issue).

This new system is like a full-body MRI that lives inside the patient. It allows engineers to:

1. See the invisible: Spot tiny delays before they cause a crash.
2. Know the cause: Tell the difference between a power problem and a wiring problem.
3. Fix it smartly: Instead of shutting down the whole city to fix one street, they can apply the exact right fix.

In Summary:
This paper presents a way to put a "smart, non-intrusive traffic camera" inside a computer chip. It watches how data moves in real-time, uses statistics to understand the "mood" of the traffic, and can tell the difference between a city-wide power outage and a single broken traffic light. This helps make computers faster, more reliable, and easier to manage.

Technical Summary

Here is a detailed technical summary of the paper "In-Situ Timing Diagnosis of PDN and Configuration-Upset-Induced Routing Delay Degradation in SRAM-based FPGAs" by Mostafa Darvishi.

1. Problem Statement

Timing predictability in SRAM-based FPGAs is increasingly challenged by interconnect delays and variability. Two primary physical mechanisms cause timing degradation in deployed systems, but they are difficult to distinguish using conventional methods:

• Power-Distribution-Network (PDN) Marginality: Transient or sustained voltage droops caused by high switching activity lead to globally correlated delay shifts across large regions of the fabric. These shifts are typically smooth and reversible.
• Configuration-Induced Routing Perturbations: Caused by Single-Event Upsets (SEUs) or configuration errors, these introduce unintended parasitic connections in the routing fabric. This results in localized, topology-dependent delay increases that accumulate over time and increase timing variance.

The Gap: Existing in-situ timing monitors (e.g., ring oscillators, critical-path sensors) typically provide binary pass/fail indicators or aggregate global metrics. They lack the spatial resolution and statistical depth to differentiate between global PDN stress and localized routing anomalies, leaving designers without visibility into the physical origin of timing failures.

2. Methodology

The paper proposes a scalable, non-intrusive, in-situ timing diagnosis architecture that operates concurrently with a user design. The methodology relies on three core components:

A. Architecture Design

• Non-Intrusive Delay Taps (DTs): Instead of inserting logic into functional paths, the system exploits the inherent fan-out capability of FPGA switch matrices. Buffered replicas of routed signals are extracted at switch-matrix boundaries without altering the original routing or loading the functional net.
• Distributed Delay Monitoring Elements (DMEs): These units perform phase-swept sampling. They sample the tapped signal using a clock whose phase is systematically shifted relative to the functional clock.
• Statistical Output: Rather than measuring absolute delay, DMEs accumulate Bit-Error-Rate (BER) statistics over observation windows. This generates a BER-versus-phase profile, which statistically represents the timing distribution (mean delay and variance) of the signal transition.
• Centralized Control: A Delay and Control Network (DCN) coordinates phase sweeps and aggregates low-bandwidth statistical summaries from distributed DMEs for analysis.

B. Experimental Setup

• Platform: Implemented on an AMD/Xilinx XCZU7EV (Zynq UltraScale+ MPSoC).
• Design Under Test (DUT): A streaming 64-tap, 16-bit FIR filter to ensure realistic routing utilization and switching activity.
• Stressors:
  • PDN Stress: An on-chip "stressor" block (LFSRs and DSP MAC units) generates high switching activity to induce voltage droop.
  • Routing Perturbation: Controlled configuration bits are toggled to enable parasitic fan-out branches, emulating the electrical effects of routing upsets (increased resistance/capacitance) without requiring external radiation sources.
• Measurement: Phase-swept BER profiling is performed under baseline, PDN-stressed, and routing-perturbed conditions.

3. Key Contributions

1. Mechanism Differentiation: The framework successfully distinguishes between PDN-induced and routing-induced degradation based on distinct statistical signatures:
   • PDN Effects: Produce a rigid horizontal shift in the BER curve (mean delay change) with minimal change in variance. The effect is spatially correlated across the fabric.
   • Routing Effects: Produce both a shift in mean delay and a significant broadening of the BER curve (increased variance/spread). The effect is localized and decorrelates rapidly with distance.
2. Spatial Correlation Analysis: The paper introduces the use of 2D correlation heatmaps and spatial correlation coefficients to visualize how timing variations propagate. PDN effects show high correlation over large distances, while routing perturbations show rapid decorrelation.
3. Non-Intrusive Implementation: The architecture requires no external instrumentation, radiation facilities, or modification of the functional design's placement/routing. It utilizes standard FPGA resources (LUTs, Flip-Flops, BUFGs) with minimal overhead.
4. Probabilistic Timing Characterization: Moves beyond binary timing margins to extract full probabilistic delay distributions (CDFs), enabling the detection of subtle degradation trends before functional failure occurs.

4. Experimental Results

• Resource Overhead: A deployment with 32 DMEs consumes approximately 1.4% of the FPGA's logic resources (LUTs/Flip-Flops), demonstrating high scalability.
• Resolution: The system achieves a phase resolution of ~15–20 ps and an effective timing accuracy of ±20 ps.
• Differentiation Validation:
  • PDN Stress: Results showed a uniform delay shift ($\Delta\mu$) across all monitored locations with negligible change in standard deviation ($\Delta\sigma \approx 0$).
  • Routing Perturbation: Results showed location-dependent delay shifts and a consistent increase in timing spread ($\Delta\sigma > 0$).
• Spatial Analysis: Correlation heatmaps confirmed that PDN-induced shifts are globally coherent, whereas routing-induced perturbations are highly localized, validating the ability to map degradation sources to physical topology.

5. Significance and Implications

• Reliability Assessment: Enables real-time diagnosis of whether a timing violation is due to a global power issue (solvable by voltage/frequency scaling) or a localized routing fault (requiring partial reconfiguration or path relocation).
• Design-for-Reliability (DfR): Provides a foundation for adaptive systems that can dynamically respond to specific degradation mechanisms, improving system longevity in radiation-prone or high-stress environments.
• CAD and Architecture: The findings suggest that current static timing analysis (STA) models may be insufficient for capturing spatially localized routing variability. The data supports the development of CAD tools that incorporate spatial correlation and in-situ feedback for more accurate timing closure.
• Scalability: The modular, distributed nature of the architecture allows it to scale to large FPGA fabrics without creating routing congestion or timing bottlenecks.

In conclusion, this paper establishes a practical, scalable framework for in-situ timing diagnosis that bridges the gap between physical routing behavior and system-level reliability management, offering a new level of observability into the "black box" of FPGA interconnects.