A 0.5-V Linear Neuromorphic Voltage-to-Spike Encoder Using a Bulk-Driven Transconductor

This paper presents a 0.5-V ultralow-power linear neuromorphic voltage-to-spike encoder fabricated in TSMC 0.18-µm CMOS that achieves near-linear conversion with less than 5.6% deviation by combining a tail-less bulk-driven transconductor with a DPI-based LIF neuron.

The Gist

Imagine you are trying to translate a human whisper into a series of Morse code clicks. That is essentially what this paper describes, but instead of a human whisper, it's an electrical signal, and instead of Morse code, it's "spikes" (tiny electrical bursts) that a computer brain (neuromorphic chip) can understand.

Here is the story of how the researchers built a tiny, ultra-efficient translator, broken down into simple concepts.

1. The Big Problem: The "Whisper" is Too Faint

Modern computers are great, but they are energy-hungry. They usually take a smooth, continuous signal (like a sound wave or a light level), chop it up into digital numbers (0s and 1s) using a heavy machine called an Analog-to-Digital Converter (ADC), and then process it. This takes a lot of battery power.

Neuromorphic engineers want to skip the middleman. They want to turn the smooth signal directly into "spikes" (events), just like our biological brains do. But there's a catch: to do this on a tiny, battery-powered chip, the circuit needs to run on extremely low voltage (0.5 Volts). That's like trying to run a car engine on a single AA battery. Most standard electronics simply won't work at that low power.

2. The Solution: A Two-Part Translator

The researchers built a two-stage machine to solve this. Think of it as a Translator followed by a Messenger.

Part A: The Translator (The Linear Transconductor)

The Job: Turn a smooth voltage (the input) into a smooth current (the fuel).
The Challenge: In the world of tiny electronics, turning voltage into current is usually messy and non-linear. It's like trying to pour water from a bucket into a funnel, but the funnel is shaped weirdly, so the water splashes everywhere instead of flowing straight.

The Magic Trick:

• The "Tail-less" Team: Usually, these circuits need a "tail" (a constant current source) to work, but that eats up too much voltage. The researchers removed the tail and used a special trick called Bulk-Driven technology. Imagine instead of pushing a car from the back (the gate), you push it from the side (the bulk/body). It's a weaker push, but it works when the engine is barely running.
• The "Anti-Noise" Net: Because pushing from the side is tricky, the signal gets distorted. To fix this, they built a "linearization network." Think of this as a noise-canceling headphone for electricity. It detects the distortion (the splashing water) and generates an opposite distortion to cancel it out, leaving a perfectly straight, clean flow of current.

Part B: The Messenger (The LIF Neuron)

The Job: Take that smooth current and turn it into a rhythm of spikes.
The Mechanism: This part is a Leaky Integrate-and-Fire (LIF) neuron.

• The Bucket: Imagine a bucket with a small hole in the bottom (the "leak").
• The Rain: The current from Part A is the rain pouring into the bucket.
• The Alarm: When the water level (voltage) gets high enough, a sensor trips, and the bucket dumps all its water out in a sudden splash (a "spike").
• The Reset: Immediately after the splash, the bucket is emptied and starts filling up again.

The Result: If the rain is light, the bucket fills slowly, and you get few splashes (low frequency). If the rain is heavy, the bucket fills fast, and you get many splashes (high frequency). The speed of the splashes tells the computer exactly how strong the original signal was.

3. Why is this a Big Deal?

The researchers tested their invention and found some amazing things:

• It's incredibly efficient: It runs on 0.5 Volts. That is the voltage of a single AA battery. Most chips need 1.8V or more.
• It's tiny: It fits in an area smaller than a grain of sand (0.0074 mm²).
• It's accurate: Even though it's running on such low power, the relationship between the input signal and the output spikes is almost perfectly straight (linear). If you double the input, you double the spike speed, with less than a 6% error.
• It's quiet: It uses almost no power (nanowatts), meaning a sensor using this could run for years on a tiny battery.

The Analogy Summary

Imagine you are at a concert.

• Old Way: You record the music, turn it into a digital file, send it to a computer, and the computer plays it back. This uses a lot of electricity.
• This Paper's Way: You have a tiny device on your ear. As the music gets louder, the device taps your ear faster. As it gets quieter, it taps slower. The device doesn't need to "understand" the music or convert it to numbers; it just translates the volume directly into a rhythm.

Because this translator is so efficient and works on such low power, it opens the door for smart sensors that can live in our bodies, in our clothes, or in remote places, listening to the world and talking to computers without ever needing a battery change.

Technical Summary

1. Problem Statement

Neuromorphic sensors aim to convert analog signals directly into spikes (event-based data) to bypass energy-intensive Analog-to-Digital Converters (ADCs). However, designing efficient encoders for ultra-low-power applications faces two primary challenges:

• Linearity vs. Low Voltage: Conventional gate-driven MOS transistors lose input range and linearity when operating near the threshold voltage. Achieving rail-to-rail operation and linear Voltage-to-Current (V-I) conversion at ultra-low supply voltages (e.g., 0.5 V) is difficult because subthreshold operation inherently introduces exponential nonlinearity.
• Encoding Accuracy: For accurate neuromorphic processing (e.g., spectral analysis), the conversion from input voltage amplitude to output spike firing rate must be highly linear. Existing designs often suffer from significant distortion or require higher supply voltages, limiting their use in energy-constrained biomedical or vision systems.

2. Methodology

The authors propose a two-stage encoder architecture operating at a 0.5 V supply using TSMC 0.18-µm CMOS technology. The design consists of a linearized front-end transconductor and a back-end Leaky Integrate-and-Fire (LIF) neuron.

A. Linearized Bulk-Driven Transconductor

• Bulk-Driven Differential Pair: To achieve rail-to-rail input range at 0.5 V, the input stage uses a "tail-less" differential pair driven by the bulk terminals rather than the gates. In the subthreshold region, bulk-driven operation offers better linearity than gate-driven operation, albeit with reduced transconductance ($g_{m,bulk} \approx 0.2 \times g_{m,gate}$).
• Translinear Linearization Network: The inherent exponential current-voltage relationship of MOSFETs in weak inversion creates a dominant $\sinh(x)$ nonlinearity. The authors introduce a translinear network that generates internal bias voltages ($V_A$ and $V_B$) to cancel this nonlinearity. By carefully controlling the ratio of drain currents in auxiliary devices, the circuit forces the differential output current to be linearly proportional to the input voltage difference.
• Symmetry and PVT Robustness: The differential input signals are also applied to the bulk terminals of cascoded devices to minimize body-effect modulation, improving tolerance to Process, Voltage, and Temperature (PVT) variations.

B. DPI-Based LIF Neuron

• Differential Pair Integrator (DPI): The transconductor output drives a DPI front-end rather than directly charging the membrane capacitor. The DPI acts as a first-order current-mode integrator with tunable gain ($V_{tu}$) and leak conductance ($V_{lk}$).
• Linearization of Current-to-Spike: The DPI is biased to operate in a specific window where the membrane charging current becomes approximately constant, linearizing the integration phase.
• Spike Generation: When the membrane voltage ($V_{mem}$) crosses a threshold, a positive-feedback loop (M4–M6) triggers a regenerative spike. An inverter chain produces a full-swing output spike, and a reset mechanism (M12) discharges the membrane capacitor for the next cycle.

3. Key Contributions

• Ultra-Low Voltage Operation: The circuit operates successfully at 0.5 V, a significant reduction compared to standard neuromorphic designs, enabling extreme energy efficiency.
• High Linearity at Subthreshold: The combination of bulk-driven inputs and a translinear correction network achieves near-linear V-to-I conversion, suppressing the dominant $\sinh$ nonlinearity typically found in subthreshold circuits.
• Linear V-to-F Encoding: The system achieves a linear relationship between input voltage and output firing rate (Voltage-to-Firing rate), which is critical for accurate signal representation in rate-coded neuromorphic systems.
• Compact and Efficient: The design eliminates the need for an ADC, reducing area and power consumption significantly.

4. Experimental Results

The encoder was fabricated and tested with the following results:

• Process & Supply: TSMC 0.18-µm CMOS, $V_{DD} = 0.5$ V.
• Linearity: Over an input range of 0.1 V to 0.4 V, the Voltage-to-Firing rate conversion exhibits a maximum deviation of less than 5.6% from a linear fit.
• Power Consumption: The circuit consumes between 22 nW and 180 nW, depending on the reference current ($I_{ref}$) and bias settings.
• Area: The total chip area is 0.0074 mm² (Neuron: $71.5 \times 49.7 \mu m^2$; Transconductor: $70.9 \times 54.2 \mu m^2$).
• Bandwidth: With appropriate biasing, the linear firing range supports input signal bandwidths up to 8 kHz (with spike rates $>40$ kHz), suitable for biological time-scale applications.
• Distortion: Total Harmonic Distortion (THD) for the transconductor ranges from 1.76% to 7.2% across the tested reference current range (2–27 nA).

5. Significance

This work demonstrates a viable path toward ultra-low-power, event-based sensing for applications such as implantable biomedical devices and event-driven vision systems. By achieving high linearity at 0.5 V without an ADC, the encoder significantly reduces the energy per spike and silicon area. The successful suppression of nonlinearity in the subthreshold region using bulk-driven techniques and translinear networks provides a robust design methodology for future low-voltage neuromorphic integrated circuits.