76 papers
Nemo is a novel flash cache design that reduces application-level write amplification for tiny-object workloads by intentionally increasing hash collisions to improve set fill rates, while simultaneously maintaining high memory efficiency and low miss ratios through a bloom filter-based indexing mechanism and hybrid hotness tracking.
The paper introduces bsort, a non-comparison-based sorting algorithm that unifies the sorting of signed/unsigned integers and floating-point numbers with an asymptotic time complexity of and auxiliary space of , demonstrating competitive performance against optimized hybrid libraries for small word sizes.
This paper introduces ChatNeuroSim, an LLM-based agent framework that automates the entire Compute-in-Memory (CIM) accelerator deployment and optimization workflow—including simulation, parameter management, and design space pruning—to significantly reduce the time and effort required for design space exploration.
This paper introduces Kareto, an adaptive multi-objective optimizer that efficiently navigates the complex configuration space of tiered KV cache storage to dynamically balance cost, throughput, and latency, significantly outperforming static strategies in LLM inference services.
FormalRTL is a novel end-to-end multi-agent framework that leverages software reference models as formal specifications to enable scalable, verified, and reliable register-transfer level (RTL) code generation for complex industrial hardware designs.
This paper proposes a method to significantly reduce hardware resource requirements for matrix multiplications and convolutions by asymptotically replacing real and complex multiplications with fewer squaring operations, which are more efficient to implement in circuits.
AnalogToBi is a novel framework for automatic device-level analog circuit topology generation that combines bipartite graph representations, grammar-guided decoding, and data augmentation to achieve high validity and novelty while ensuring electrical correctness without human intervention.
This paper presents an empirical study mapping the interactions between model characteristics and prompt engineering strategies for Verilog code generation, revealing which trends generalize across diverse language models and benchmarks through controlled experiments.
This paper introduces the Hybrid Residue Floating Numerical Architecture (HRFNA), a formally verified numerical system combining carry-free residue arithmetic with lightweight exponent scaling that achieves significantly higher throughput, reduced resource usage, and improved energy efficiency on FPGAs compared to IEEE 754 standards while maintaining rigorous, bounded numerical error.
TrainDeeploy is a novel framework that enables efficient, parameter-efficient on-device fine-tuning of both CNN and Transformer models on ultra-low-power, memory-constrained RISC-V SoCs, achieving significant reductions in memory usage and computational overhead while supporting end-to-end training at the extreme edge.
The AetherFloat Family introduces a novel block-scale-free, quad-radix floating-point architecture that eliminates the hardware overhead of dynamic scaling and IEEE 754 inefficiencies, achieving significant area, power, and latency reductions in AI accelerators through explicit mantissas, base-4 scaling, and stochastic rounding.
This paper presents a data-rate-aware CNN accelerator architecture for FPGAs that utilizes multi-pixel processing and design-space exploration to optimize hardware utilization and resource efficiency across varying data rates, thereby enabling the efficient implementation of complex CNNs on a single device.
This paper reviews the landscape of ultra-low-power edge and in-sensor AI processors and empirically benchmarks a segmentation model on GAP9, STM32N6, and Sony IMX500 platforms to demonstrate that while in-sensor processing offers superior energy-delay performance, different architectures provide distinct trade-offs between latency, energy efficiency, and power budgets.
KernelCraft introduces the first benchmark evaluating agentic LLM systems that use feedback-driven workflows to automatically generate and optimize low-level kernels for emerging hardware with novel ISAs, demonstrating their ability to produce valid, high-performance code that rivals or exceeds traditional compiler baselines.
The paper introduces EPIC, a hardware- and physics-co-guided distributed scientific machine learning framework that significantly reduces communication latency and energy consumption while preserving physical fidelity by performing lightweight local encoding and physics-aware decoding with cross-attention for tasks like full-waveform inversion.
This paper introduces the inequality to demonstrate that Mixture-of-Experts (MoE) models suffer from a structural "double penalty" of routing fragmentation and memory constraints during inference, often rendering them significantly less efficient than quality-matched dense models for long-context serving despite their training-time FLOP advantages.
This paper introduces DendroNN, a novel dendrocentric neural network that leverages non-differentiable sequence detection and a rewiring phase to efficiently classify event-based spatiotemporal data, achieving competitive accuracy with up to 4x higher energy efficiency than state-of-the-art neuromorphic hardware through a dedicated asynchronous digital architecture.
This paper proposes a cost-effective framework that leverages structurally informative but functionally imperfect LLM-generated RTL to train netlist representation models, effectively overcoming data scarcity and outperforming methods reliant on scarce high-quality labeled datasets.
This paper presents a systematic layer-wise and block-wise sensitivity analysis of NVFP4 and MXFP4 quantization across three Qwen2.5 model scales, revealing that MLP up- and down-projection layers are the most sensitive components while sensitivity patterns vary by format and model depth rather than being confined to final blocks.
This paper reviews FPGA-based AI accelerators for deep learning, highlighting their advantages over ASICs and GPUs, detailing key hardware optimization techniques such as loop pipelining and quantization, and analyzing state-of-the-art designs to identify challenges for future innovations.