SFATTI: Spiking FPGA Accelerator for Temporal Task-driven Inference -- A Case Study on MNIST

This paper presents SFATTI, an FPGA-based spiking neural network accelerator generated via the open-source Spiker+ framework, demonstrating its effectiveness for low-latency, energy-efficient handwritten digit recognition on the MNIST dataset within edge computing constraints.

The Gist

Imagine you are trying to teach a robot to recognize handwritten numbers (like "7" or "3") from a photo. Usually, we teach robots using "Artificial Neural Networks" (ANNs), which are like super-fast, heavy-duty calculators that crunch every single number in the picture at once. This is powerful, but it's also like running a marathon while carrying a backpack full of bricks—it uses a lot of energy and takes up a lot of space.

This paper introduces a smarter, lighter approach called Spiking Neural Networks (SNNs). Think of an SNN not as a calculator, but as a firing squad of neurons. Instead of constantly shouting numbers, these neurons stay quiet until they have something important to say. When they do "speak," they send a tiny, quick electrical pulse called a "spike." If there's nothing new to say, they stay silent. This "event-driven" nature makes them incredibly energy-efficient, perfect for small devices like smartwatches or drones that run on batteries.

The Problem: Building the Hardware

The tricky part is that these "spiking" brains are very different from the standard computer chips we have today. Building a custom chip to handle them is usually like trying to build a custom house by hand, brick by brick, for every single design. It takes forever, requires expert architects, and is prone to mistakes.

The Solution: The "Spiker+" Factory

The authors of this paper created a tool called Spiker+. Think of Spiker+ as an automated 3D printer for robot brains.

1. The Blueprint (Training): First, you design the brain on a regular computer using Python. You teach it to recognize numbers using a special method that mimics how biological brains learn (using "surrogate gradients," which is just a fancy way of saying "we trick the computer into learning how to fire spikes").
2. The Translation (Quantization): Computers usually use very precise numbers (like 3.14159...), but tiny chips can't handle that much detail without getting huge and hot. Spiker+ acts like a translator, rounding off these numbers to simple, easy-to-handle values (like 3 or 4) so the hardware doesn't need expensive multipliers. It's like converting a complex recipe into a simple "pinch of salt" instruction that anyone can follow quickly.
3. The Construction (HDL Generation): Once the design is optimized, Spiker+ automatically writes the code (VHDL) needed to build the physical chip on an FPGA (a chip you can reprogram, like a Lego set for electronics).

The Experiment: The MNIST Challenge

The team tested this system on the MNIST dataset, which is basically a giant photo album of handwritten digits used to test AI. They wanted to see if their "3D printer" could build a robot brain that was:

• Fast: Recognizing numbers instantly.
• Efficient: Using very little battery power.
• Accurate: Getting the right answer most of the time.

The Results: A Winning Strategy

They tried many different "architectures" (different sizes and shapes of the brain).

• The Winner: They found a specific design that was the "Goldilocks" zone. It wasn't the biggest or the most complex, but it was the most efficient.
• The Analogy: Imagine two delivery trucks. One is a massive semi-truck carrying a full load of bricks (traditional AI). It moves fast but burns a lot of gas. The other is a nimble electric scooter (their SNN). It only moves when it has a package to deliver (spikes), and it stops when it doesn't.
• The Outcome: Their "scooter" design could process thousands of images per second while using a fraction of the energy. They achieved over 97% accuracy in reading the numbers, which is excellent, while keeping the power consumption incredibly low.

Why This Matters

This paper is a big deal because it removes the heavy lifting from engineers. Instead of spending months manually wiring a chip, they can now use Spiker+ to automatically generate a highly efficient, custom brain for a specific task.

In a nutshell: They built a tool that automatically designs and builds ultra-efficient, low-power robot brains that work like real biological neurons. This means we can soon have smart devices that can see, hear, and react in real-time without needing to be plugged into a wall or draining their batteries in minutes. It's a major step toward making "smart" devices that are truly "smart" about how they use energy.

Technical Summary

1. Problem Statement

Edge computing applications (e.g., image recognition, sensor fusion) require low-latency, energy-efficient inference. While traditional Artificial Neural Networks (ANNs) are widely used, they rely on dense matrix multiplications and continuous activations, which are computationally expensive and power-hungry on embedded hardware.

Spiking Neural Networks (SNNs) offer a promising alternative due to their event-driven, temporally sparse nature, mimicking biological neurons. However, deploying SNNs on hardware presents significant challenges:

• Hardware Mismatch: Conventional hardware accelerators are optimized for synchronous, dense operations, whereas SNNs are asynchronous and sparse.
• Design Complexity: Existing neuromorphic solutions (e.g., TrueNorth, Loihi) often lack flexibility or impose strict constraints on network structure. FPGA-based solutions exist but typically require extensive manual design effort, lack modularity, and are tightly coupled to specific toolchains.
• Optimization Trade-offs: There is a need to co-optimize the neural network architecture and its hardware implementation to balance accuracy, latency, and power consumption without manual HDL coding.

2. Methodology

The authors propose SFATTI, a workflow centered around the open-source Spiker+ framework. This framework enables an end-to-end flow from high-level SNN modeling to the generation of optimized FPGA hardware.

A. Workflow Overview

1. Spike Encoding: Since MNIST is a static dataset, the authors use Poisson-based rate coding to convert pixel intensities into spike trains. Each pixel intensity determines the firing probability at each timestep.
2. Network Training:
   • Surrogate Gradients: To overcome the non-differentiable nature of spikes, the framework uses surrogate gradient methods (via snnTorch) to train the network using Back-Propagation Through Time (BPTT).
   • Hardware-Aware Constraints: During training, the neuron model parameters (decay rates $\alpha$ and $\beta$) are rounded to the nearest power of two. This allows the hardware to implement exponential decay using simple binary shifts instead of costly multipliers, significantly reducing FPGA resource usage.
3. High-Level Design Space Exploration (DSE): Before hardware synthesis, the authors use Optuna to perform hyperparameter optimization on network architectures (layer sizes, neuron types) to identify promising candidates based on accuracy and algorithmic efficiency.
4. Quantization Exploration: Spiker+ performs a combinatorial sweep of bit-widths for weights, membrane potentials, and fractional precision. It uses signed two's complement fixed-point arithmetic with overflow protection to find the optimal trade-off between precision and hardware cost.
5. HDL Generation: The framework automatically generates synthesizable VHDL code. It supports various neuron models (1st-order LIF, 2nd-order LIF, Integrate-and-Fire) and configures memory blocks to match the target FPGA's Block RAM (BRAM).
6. Implementation: The generated VHDL is synthesized and mapped to a Xilinx Kintex XC7K160TFBG484-1 FPGA using Vivado.

B. Key Technical Innovations

• Power-of-Two Rounding: A specific training constraint that eliminates multipliers in the hardware by approximating decay operations as bit-shifts.
• Automated Co-Design: The seamless integration of training (Python/snnTorch) and hardware generation (Spiker+) allows for rapid exploration of the design space without manual HDL intervention.
• Sequential Processing: The architecture processes input spikes sequentially to mitigate bandwidth and memory limitations typical of low-end FPGAs, utilizing a dual-buffer interface to maintain continuous operation.

3. Key Contributions

• Open-Source Framework Integration: Demonstrated the efficacy of Spiker+ as a complete toolchain for SNN deployment, bridging the gap between software training and hardware deployment.
• Hardware-Efficient SNNs: Introduced a method to train SNNs with hardware constraints (power-of-two parameters) directly, enabling multiplier-free FPGA implementations.
• Comprehensive DSE: Conducted a systematic evaluation of multiple network configurations (varying hidden layer sizes and quantization bit-widths) to identify the optimal balance between accuracy, power, and latency.
• Challenge Participation: Successfully applied this methodology to the Digit Recognition Low Power and Speed Challenge @ ICIP 2025, validating the approach against strict edge constraints.

4. Results

The authors evaluated various configurations on the MNIST dataset (60k training, 10k test samples).

• Accuracy: The best-performing configuration (784-75-10 architecture with 10-bit weights and membrane potentials) achieved 97.86% accuracy.
• Energy Efficiency: The most energy-efficient design (highlighted in the paper) achieved 81,712.5 images per second per watt (img/s/W).
• Throughput & Latency:
  • The accelerator processes a single image in approximately 52.98 $\mu$s (at a clock frequency of ~163.9 MHz).
  • This translates to a throughput of approximately 18,875 images per second.
• Resource Utilization: All designs fit comfortably within the target FPGA resources (LUTs, Flip-Flops, BRAMs). The designs utilized no DSP blocks, relying solely on logic and memory, which is crucial for low-power edge devices.
• Trade-offs: Increasing bit-widths and hidden layer sizes improved accuracy but increased power consumption and reduced energy efficiency. The authors successfully identified a "sweet spot" where accuracy remained high (>97.5%) while minimizing power.

5. Significance and Conclusion

This work validates that task-specific, reconfigurable SNN accelerators are a viable alternative to traditional ANNs for low-power edge image processing.

• Scalability: The automated flow reduces the manual effort required to deploy SNNs, making neuromorphic computing more accessible to researchers and engineers.
• Efficiency: By leveraging the event-driven nature of SNNs and optimizing the hardware for sparse data (removing multipliers, using bit-shifts), the system achieves superior energy efficiency compared to dense ANN accelerators.
• Future Outlook: The authors note that while the current challenge focused on inference, the same framework can be extended to support on-chip learning, adaptive neurons, and fully event-based datasets (e.g., from DVS cameras), further narrowing the gap between neuromorphic theory and practical, deployable hardware.

In summary, SFATTI demonstrates that with the right toolchain and hardware-aware training strategies, SNNs can be efficiently deployed on FPGAs to meet the stringent latency and power requirements of modern edge computing applications.