Device-scaling constraints imposed by the van der Waals gap formed in two-dimensional materials

This paper reveals that while the van der Waals gap in two-dimensional materials suppresses gate leakage, it critically limits device scaling by increasing contact resistance and introducing parasitic capacitance, suggesting that "zipper-like" quasi-covalent interfaces are necessary to overcome these barriers.

The Gist

Imagine you are trying to build the ultimate, tiniest possible house for a single electron to live in. This "house" is a transistor, the fundamental building block of every computer chip. As technology advances, we want these houses to get smaller and smaller to fit more of them on a chip, making our devices faster and more powerful.

For decades, we've been shrinking these houses using silicon. But now, scientists are looking at 2D materials (like a single sheet of paper made of atoms, such as Molybdenum Disulfide) as the new, ultra-thin walls for these houses. They are perfect because they are so thin that we can control the electricity flowing through them very precisely.

However, this paper reveals a hidden "ghost in the machine" that threatens to ruin our plans: The Van der Waals Gap.

The Problem: The Invisible Air Gap

When you build a house, you want the walls to be perfectly flush against the foundation and the roof. If you put a tiny, invisible layer of air between the wall and the roof, things go wrong.

In the world of 2D materials, when you try to stick a gate (the switch that controls the electron) or a metal contact (the door for electrons to enter/exit) onto the 2D sheet, they don't bond tightly like glue. Instead, they hover slightly apart, separated by a microscopic vacuum gap (about 1.4 Angstroms wide—roughly the size of a single atom).

The authors call this the Van der Waals (vdW) gap. It's like trying to stack two sheets of glass that are slightly repelling each other; they never quite touch.

The Double-Edged Sword

This gap creates a confusing situation with two opposing effects:

1. The Good News: The "Security Guard"
Think of the gate as a security guard trying to stop electrons from leaking out of the house when they shouldn't. Because the gap is essentially a vacuum, it acts as a very strong barrier. It makes it very hard for electrons to tunnel through and leak out.

• Analogy: It's like putting a thick, reinforced steel door in front of a weak wooden door. It stops the burglars (leakage) very well.

2. The Bad News: The "Traffic Jam"
While the gap stops leaks, it also creates two major problems for the house's performance:

• The Insulation Problem: The gap is like a layer of air. Air is a terrible insulator compared to the high-tech materials we use. This "air layer" adds extra thickness to the wall, making the electrical control weaker. It's like trying to push a heavy door, but there's a thick cushion of foam in the way. You have to push much harder (more voltage) to get the same result.
• The Contact Problem: When electrons try to enter the house through the metal door (source/drain contacts), they have to jump across this tiny air gap. This creates a massive traffic jam. The resistance goes up, and the electrons can't get in or out fast enough.

The "Zipper" Solution

The paper argues that we cannot just ignore this gap. Even though it's tiny, it adds up to a significant "penalty" in our design budget. If we keep using standard methods, we simply won't be able to shrink the transistors enough to meet the goals set for the year 2030 and beyond.

So, what's the fix? The authors suggest a Zipper Interface.

Imagine instead of just stacking two sheets of glass with a gap, you design them so they have little hooks and loops that interlock perfectly, like a zipper.

• The Analogy: Instead of a loose stack, you create a "quasi-covalent" bond. The materials interlock just enough to close the air gap completely, but without creating messy, broken bonds (dangling bonds) that would ruin the electronics.
• The Result: The "air gap" disappears. The wall becomes solid and continuous. The insulation becomes perfect, and the traffic jam at the door vanishes.

Why This Matters

The paper does a deep dive into the math to show that for most current materials (like high-tech ceramics), this invisible gap is the reason they fail to meet future performance targets. It's not that the materials are bad; it's that the gap ruins their potential.

In summary:
We are trying to build the smallest, fastest computers possible using 2D materials. But these materials have a habit of leaving a tiny, invisible air gap between them and their neighbors. This gap acts like a traffic jam and a weak wall, preventing us from making the chips fast enough. The solution is to engineer these materials to "zipper" together, closing the gap and unlocking the true potential of the next generation of electronics.

Technical Summary

1. Problem Statement

As transistor dimensions shrink into the single-digit nanometer regime (5–10 nm), two-dimensional (2D) semiconductors (e.g., MoS₂) are considered promising candidates due to their excellent electrostatic control. However, a critical bottleneck exists in the interface between these 2D channels and their gate dielectrics or source/drain contacts. Unlike Silicon, which forms strong covalent bonds with SiO₂, 2D materials interact with other materials primarily through weak van der Waals (vdW) forces.

This interaction creates an interfacial vdW gap (a vacuum-like region of ~1.4 Å) that was previously often overlooked in theoretical screening. The paper addresses the dual impact of this gap:

1. Electrostatic Penalty: The gap acts as a low-permittivity ($\kappa \approx 2$) series capacitor, increasing the Equivalent Oxide Thickness (EOT) and degrading gate control.
2. Tunneling Barrier: The gap acts as a high-barrier tunneling layer, suppressing gate leakage currents.
3. Contact Resistance: The gap at metal contacts significantly increases source/drain resistance, potentially violating International Roadmap for Devices and Systems (IRDS) targets.

The central question is whether the leakage suppression benefit of the vdW gap outweighs its electrostatic and contact resistance penalties for future scaling nodes (beyond 2030).

2. Methodology

The authors employed a multi-scale approach combining first-principles calculations, analytical modeling, and quantum transport simulations:

• Ab Initio Calculations (DFT): Used Vienna Ab initio Simulation Package (VASP) to calculate equilibrium interface geometries, binding energies, and charge redistribution for various insulator–MoS₂ stacks (e.g., hBN, SrTiO₃, HfO₂).
• Permittivity Profiling: Developed a spatially resolved effective permittivity profile, $\kappa(z)$, to quantify the low-permittivity nature of the vdW gap and its contribution to the total EOT.
• Tunneling Modeling:
  • Analytical: Used the Wentzel–Kramers–Brillouin (WKB) approximation within the Tsu–Esaki framework to model tunneling currents through the insulator and the vdW gap.
  • Quantum Transport: Validated analytical models using Non-Equilibrium Green's Function (NEGF) simulations coupled with DFT for graphene–hBN–graphene and Au–MoS₂ contacts.
• Figure of Merit (FoM): Defined a new FoM for insulators ($\text{FoM} = \frac{\kappa_{ins} \beta_{ins}}{\kappa_{SiO2} \beta_{SiO2}}$) to benchmark materials based on their ability to suppress leakage per unit of EOT, explicitly accounting for the vdW gap.
• Scaling Analysis: Integrated channel capacitance (quantum capacitance and charge centroid effects), vdW gap capacitance, and tunneling leakage to determine the minimum achievable EOT for various materials against IRDS 2030+ targets.

3. Key Contributions

A. Quantification of the vdW Gap

• The study establishes that the equilibrium vdW gap thickness is consistently ~1.4 Å across various insulator–MoS₂ interfaces.
• This gap has an effective permittivity of $\kappa_{vdW} \approx 2$, significantly lower than high-$\kappa$ dielectrics.
• Consequently, the vdW gap imposes a fixed EOT penalty of ~2.7 Å (intrinsic to the interface), regardless of the bulk insulator thickness.

B. The Trade-off: Leakage vs. Electrostatics

• Leakage Suppression: The vdW gap acts as a vacuum-like barrier, reducing tunneling current by orders of magnitude (e.g., ~260x suppression in hBN stacks).
• Electrostatic Degradation: While leakage is reduced, the low-$\kappa$ gap adds significant series capacitance.
• Net Result: For low-$\kappa$ insulators (like hBN), the leakage suppression can slightly improve the minimum EOT. However, for high-$\kappa$ insulators (like SrTiO₃ or HfO₂), the electrostatic penalty dominates. The vdW gap prevents these materials from reaching their theoretical EOT limits, often pushing the achievable EOT above the IRDS target of <6 Å (for the insulator portion).

C. Contact Resistance Limits

• The vdW gap at metal–semiconductor contacts introduces a tunneling barrier that drastically increases contact resistance ($R_c$).
• Even a sub-nanometer gap causes contact resistance to exceed the IRDS target of 180 $\Omega\mu$m for beyond-2030 nodes, unless the gap is eliminated or the semiconductor has extremely high degeneracy.

D. The "Zipper" Solution

• The paper identifies "zipper-like" interfaces (e.g., $\beta$-Bi₂SeO₅–Bi₂O₂Se) as a viable solution. These interfaces feature quasi-covalent bonding that eliminates the vacuum gap without creating dangling bonds.
• Experimental verification shows such interfaces can achieve EOT < 5 Å and maintain high mobility, bypassing the vdW scaling bottleneck.

4. Key Results

• EOT Budget Breakdown: For IRDS targets (Total CET < 9 Å), the MoS₂ channel contributes ~3 Å. This leaves only <6 Å for the combined insulator and vdW gap.
  • With a standard vdW gap (~2.7 Å EOT contribution), the insulator itself must have an EOT of <3.3 Å.
  • If the gap is slightly enlarged due to fabrication imperfections (e.g., 1.5x), the insulator EOT budget drops to <1 Å, which is practically impossible.
• Material Screening:
  • SrTiO₃ (STO): Despite a bulk $\kappa \approx 270$, the combination of interfacial dead layers and the vdW gap raises its minimum achievable EOT to ~7 Å, failing IRDS targets.
  • hBN: Shows a net benefit from the vdW gap (leakage suppression outweighs capacitance penalty), but its low bulk $\kappa$ limits its utility for aggressive scaling.
  • $\beta$-BSO–BOS: The only candidate shown to meet sub-5 Å EOT targets by eliminating the vdW gap.
• FoM Threshold: The study derives a condition where the vdW gap is beneficial only if the insulator's FoM is low ($\text{FoM} \lesssim 1$). For high-performance insulators ($\text{FoM} > 5$), the vdW gap is a severe liability.

5. Significance and Implications

• Paradigm Shift in Screening: The paper challenges the prevailing assumption that high bulk permittivity and large band gaps are sufficient for next-generation gate dielectrics. It demonstrates that interfacial physics (vdW gaps and dead layers) are the dominant constraints, not bulk material properties.
• Design Guidelines: Future 2D transistor design must prioritize interface engineering over bulk material selection. Simply stacking high-$\kappa$ materials on 2D channels is insufficient; the interface must be chemically modified to remove the vacuum gap.
• Path Forward: The identification of "zipper-like" interfaces provides a concrete roadmap for scalable 2D electronics. It suggests that native oxide approaches or engineered covalent bonding are essential to realize the full potential of 2D semiconductors in logic applications.
• Generalizability: The analytical framework developed (incorporating vdW gaps and dead layers into FoM and EOT calculations) is applicable to gate-all-around (GAA) nanowires and other quasi-1D architectures, providing a baseline for assessing intrinsic scaling limits in the presence of interfacial non-idealities.

In conclusion, the vdW gap is a fundamental scaling bottleneck for 2D electronics. While it offers a "free" leakage reduction, its electrostatic cost is too high for high-performance logic unless specific interface engineering strategies (like zipper bonds) are employed to eliminate the gap entirely.