Modelling the Impact of Device Imperfections on Electron Shuttling in SiMOS devices

This paper employs full 3D simulations to demonstrate that while SiMOS electron shuttling is robust against many fabrication imperfections, it is highly sensitive to oxide-interface defects and low gate voltages, which can cause a collapse from efficient conveyor-belt to inefficient bucket-brigade transport modes.

The Gist

Imagine you are trying to move a very delicate, precious marble (an electron) across a long, bumpy table (a silicon chip) to get it from Point A to Point B. In the world of quantum computing, this "marble" holds information, and if it gets jostled too hard or falls off the table, the information is lost.

This paper is about figuring out the best way to move that marble on a specific type of table called a SiMOS device (Silicon-Metal-Oxide-Semiconductor). While scientists have already mastered moving marbles on a different, smoother table (Si/SiGe), the SiMOS table is trickier because it's built with standard factory materials and has more "rough spots."

Here is the breakdown of their findings using simple analogies:

1. The Two Ways to Move the Marble

The researchers compared two methods for moving the electron:

• The Bucket-Brigade (The Old Way): Imagine a line of people passing a bucket of water down the line. You tip the bucket from one person to the next. If you tip it too fast or too hard, water spills. In quantum terms, this is risky because if you make a mistake, the electron might go backward or get stuck.
• The Conveyor Belt (The New Way): Imagine the marble sitting in a moving bowl that glides smoothly along a track. The bowl never stops; it just flows. This is the "Conveyor-Belt" method. It's much smoother and safer, but it requires the track to be perfectly shaped.

2. The Problem: The "Layered" Table

The SiMOS device is built in layers, like a sandwich. The researchers found a hidden trap in the design:

• The Voltage Trap: To make the conveyor belt move, they apply electricity to "gates" (like buttons) on top. They discovered that if the voltage is too low, the "sandwich" layers block the electricity in a weird way.
• The Result: Instead of a smooth conveyor belt, the system accidentally turns back into the risky "Bucket-Brigade" mode. The marble gets jostled, jumps around, and gets excited (like a shaken soda can).
• The Fix: They found that if you turn up the voltage just a little bit (like tightening a screw), the conveyor belt starts working smoothly again.

3. The Obstacles on the Track

The real world isn't perfect. The paper tested three main types of "potholes" on the track:

• Rough Surfaces (Interface Roughness):

  • The Analogy: Imagine the table isn't perfectly flat; it has microscopic bumps and valleys, like sandpaper.
  • The Finding: Surprisingly, the conveyor belt is very robust against this. Even if the table is quite bumpy, the electron stays in the bowl and keeps moving. The "roughness" didn't cause the marble to fall off.

• Misaligned Buttons (Gate Imperfections):

  • The Analogy: Imagine the buttons on the conveyor belt are slightly crooked or different sizes because the factory machine wasn't 100% perfect.
  • The Finding: The system is very forgiving. Even if the buttons are misaligned by up to 30%, the smooth motion of the belt averages out the errors. The electron doesn't care much about the crooked buttons.

• The "Greedy" Spots (Charge Defects):

  • The Analogy: This is the biggest danger. Imagine there are sticky spots or magnets on the table.
    • Negative Defects (Repulsive): These are like a repulsive force field. They push the marble away, making it wobble, but usually, the marble keeps moving.
    • Positive Defects (Attractive): These are like sticky traps or a deep hole. If the marble rolls near one, it gets stuck.
  • The Finding: If the voltage is too low, the electron gets permanently trapped by these "sticky spots" and never reaches the destination. However, if you increase the voltage (make the conveyor belt move faster and with more force), the electron can break free from the trap.
  • The Catch: Even if it breaks free, it might be "shaken up" (orbitally excited) on the way out. But the good news is that this shaking usually doesn't destroy the quantum information inside the marble.

4. The Bottom Line

The paper concludes that SiMOS devices are actually ready for this task, provided we tune them correctly.

• Don't use low power: If you run the system at low voltage, it collapses into the messy "bucket-brigade" mode, and sticky traps will steal your electrons.
• Use higher power: By increasing the voltage, you create a strong, smooth "conveyor belt" that can ignore the bumpy table, the crooked buttons, and even break electrons free from sticky traps.

In summary: The researchers built a digital simulation of a quantum chip and proved that with the right settings, we can reliably "shuttle" electrons across silicon chips, paving the way for building massive, scalable quantum computers using standard factory techniques.

Technical Summary

1. Problem Statement

Silicon-based spin qubits are a leading candidate for scalable quantum computing due to their compatibility with industrial fabrication and long coherence times. While high-fidelity electron shuttling (transporting electrons between quantum dots) has been demonstrated in Silicon-Germanium (Si/SiGe) heterostructures, progress in Silicon-Metal-Oxide-Semiconductor (SiMOS) devices lags behind.

The primary challenge in SiMOS is the absence of a germanium buffer layer. In Si/SiGe, this buffer separates electrons from the oxide layer, providing electrostatic screening against defects. In SiMOS, electrons are confined directly against the abrupt Si/SiO$_2$ interface, making them highly susceptible to:

• Interface roughness: Atomic-scale irregularities at the Si/SiO$_2$ boundary.
• Gate fabrication imperfections: Misalignments and width variations in the gate stack.
• Charge defects: Trapped charges in the oxide (e.g., $E'$ centers) or at the interface (e.g., $P_b$ centers), which can distort the potential landscape or capture electrons.

The paper aims to determine if reliable, high-fidelity "conveyor-belt" shuttling is feasible in SiMOS architectures despite these imperfections, identifying the operating regimes where transport remains adiabatic and lossless.

2. Methodology

The authors performed full 3D numerical simulations of a realistic SiMOS conveyor-belt shuttling device, advancing beyond previous 2D models.

• Device Model: A quantum dot array with side-gates for lateral confinement and "clavier-gates" arranged in an ABCDABCD configuration. The gates are separated by oxide layers (15 nm for side-gates, 5 nm between gate layers), mimicking realistic deposition processes.
• Physics Equations:
  • Poisson Equation: Solved to determine the electrostatic potential landscape ($V_g$) generated by gate voltages, including the effects of oxide screening and charge traps.
  • Time-Dependent Schrödinger Equation (TDSE): Solved to track electron dynamics. The Hamiltonian includes the effective mass tensor and the time-varying potential.
• Numerical Techniques:
  • Spectral Projection Method: The primary solver used to separate rapid dynamical phases from slow amplitude variations, allowing for larger timesteps and efficient parameter sweeps.
  • Split-Operator Method: Used as a high-accuracy benchmark to validate the spectral projection approach.
  • Defect Modeling: Interface roughness was modeled using a power-law Power Spectral Density (PSD) derived from an Autocorrelation Function (ACF). Charge defects were modeled as point charges ($\pm e$) located at the interface or within the oxide.
• Metrics:
  • Charge Loss ($P_L$): Probability of the electron escaping the conveyor.
  • Adiabaticity ($F$): Fidelity of the shuttled wavefunction with the instantaneous ground state ($F = |c_0|^2$).

3. Key Contributions & Results

A. The "Bucket-Brigade" Transition

A critical finding is the transition from conveyor-belt mode (smooth transport in a single moving potential minimum) to bucket-brigade mode (adiabatic Landau-Zener transitions between dots) at low clavier-gate voltages ($V_c \approx 100$ mV).

• Cause: In multi-layer gate architectures, gates in the third layer (B and D) experience additional oxide screening (5 nm) compared to the second layer (A and C). At low $V_c$, this results in significantly weaker confinement under gates B and D, creating potential barriers.
• Effect: The electron tunnels across these barriers rather than riding a smooth wave, causing massive orbital excitation and loss of adiabaticity.
• Solution: Increasing $V_c$ to $\ge 150$ mV restores the conveyor-belt mode by deepening the potential wells sufficiently to overcome the screening effect.

B. Impact of Interface Roughness

• Finding: Interface roughness (RMS up to 0.9 nm) does not cause significant charge loss.
• Fidelity: Ground state fidelities remain above 99% for most parameter combinations, even with high roughness.
• Conclusion: While roughness increases orbital excitations slightly, it is not a primary barrier to SiMOS shuttling provided the confinement voltage is sufficient.

C. Impact of Gate Fabrication Imperfections

• Finding: The system is robust against gate misalignments and width variations up to 30%.
• Mechanism: The smooth potential landscape created by neighboring gates averages out local geometric asymmetries.
• Caveat: At very strong confinement ($V_s = -1500$ mV), the electron wavefunction becomes small enough to "resolve" the misalignment, leading to increased diabatic transitions. However, standard industrial lithography (nanometer precision) is well within the tolerable range.

D. Impact of Charge Defects (Critical Finding)

The nature of the charge defect (positive vs. negative) dictates the failure mode:

• Negative Defects: Act as repulsive barriers. They deform the wavefunction but generally do not cause charge loss. Fidelity remains high ($>99\%$) unless the confinement is extremely weak (inducing bucket-brigade behavior) or the defect is in a region of high potential gradient.
• Positive Defects: Act as attractive traps. This is the most significant obstacle.
  • Low Voltage ($V_c = 100$ mV): The electron is permanently captured by the trap, leading to complete transport failure.
  • Intermediate Voltage ($V_c = 250$ mV): The electron may partially escape, resulting in delocalization over the trap-conveyor system (partial loss).
  • High Voltage ($V_c = 500$ mV): The electron can escape the trap, but the process induces significant orbital excitation (fidelity drops to 0–60%) due to non-adiabatic transitions as the electron is pulled out of the deep trap.

4. Significance and Implications

1. Operating Regimes Defined: The paper establishes a "safe" operating window for SiMOS shuttling:
   • Clavier Voltage ($V_c$): Must be $\ge 150$ mV (ideally $\sim 500$ mV) to avoid the bucket-brigade collapse and ensure sufficient screening against defects.
   • Side-Gate Voltage ($V_s$): Must be optimized to balance confinement strength against the ability of the wavefunction to deform around negative defects.
2. Feasibility of SiMOS Shuttling: Despite the lack of a buffer layer, the study proves that conveyor-belt shuttling is viable in SiMOS if the device is operated at higher voltages to mitigate oxide screening and trap capture.
3. Defect Mitigation: The results highlight that positive charge traps are the limiting factor. This suggests that future SiMOS quantum processors must prioritize fabrication techniques that reduce positive interface trap densities (e.g., Hydrogen Resist Lithography or specific annealing processes).
4. Spin-Qubit Context: While the study focuses on orbital degrees of freedom, the authors note that orbital excitations can lead to spin-flips via spin-orbit coupling. However, given the small spin-orbit admixture in silicon ($\sim 10^{-3}$), spin-conserving decay channels are expected to dominate, meaning the orbital fidelity is the primary bottleneck.

Conclusion

This work provides the first comprehensive 3D modeling of electron shuttling in SiMOS devices. It identifies that while interface roughness and gate misalignment are manageable, oxide screening effects at low voltages and positive charge traps are the critical challenges. By operating at higher clavier-gate voltages ($\sim 500$ mV), reliable, near-adiabatic charge transport can be achieved, paving the way for scalable, industry-compatible silicon quantum processors.