KANELÉ: Kolmogorov-Arnold Networks for Efficient LUT-based Evaluation

This paper introduces KANELÉ, a framework that leverages the spline-based structure of Kolmogorov-Arnold Networks to enable efficient, low-latency FPGA deployment via lookup tables, achieving significant speedups and resource savings while matching or surpassing existing LUT-based architectures.

The Gist

Imagine you have a massive, super-smart calculator that needs to solve complex math problems instantly. In the world of artificial intelligence, this calculator is usually built like a giant factory of assembly lines (called MLPs or Multi-Layer Perceptrons). These factories are great, but they are heavy, slow to start up, and consume a lot of electricity.

Now, imagine a new type of calculator called KAN (Kolmogorov-Arnold Network). Instead of a factory with assembly lines, a KAN is more like a giant, organized library of cheat sheets.

Here is the story of KANELÉ, the new framework that makes these "cheat sheet" calculators run on tiny, powerful chips called FPGAs (Field-Programmable Gate Arrays).

1. The Problem: The "Heavy Factory" vs. The "Cheat Sheet"

Traditional AI models (MLPs) work by doing millions of multiplications and additions. It's like trying to bake a cake by mixing every single ingredient from scratch every time you want a slice. It's accurate, but it's slow and uses a lot of energy.

KANs are different. They are based on a mathematical theorem that says: "Any complex curve can be built by stacking simple, wiggly lines on top of each other."
Instead of doing heavy math, a KAN just looks up the answer on a pre-drawn graph. It's like having a Look-Up Table (LUT). You ask, "What's the answer for input X?" and the table instantly says, "Y!"

The Catch: Until now, trying to run these "cheat sheet" KANs on hardware was a disaster. The old attempts were like trying to carry a library of books in a backpack; they were too heavy, too slow, and used too much battery. One previous study even said, "KANs are too expensive for hardware."

2. The Solution: KANELÉ (The "Pastry" Framework)

The authors of this paper created KANELÉ (named after a French pastry that is compact but has many delicious layers). They figured out how to turn the KAN "cheat sheets" into something that fits perfectly inside a tiny FPGA chip.

Here is how they did it, using simple analogies:

A. The "Digital Menu" (Quantization)

Imagine a restaurant menu. If the menu lists prices like "$12.345678," it's hard to read quickly. But if you round it to "$12," it's instant.
KANELÉ takes the smooth, complex curves of the KAN and turns them into a digital menu with rounded prices. They use a technique called "Quantization" to force the math to use simple numbers (like 3-bit or 6-bit numbers) instead of complex decimals. This makes the "cheat sheets" tiny and easy to store.

B. The "Trash Can" (Pruning)

In a library, not every book is useful. Some are just blank pages.
KANELÉ has a smart "Trash Can" feature called Pruning. It looks at every single "cheat sheet" (activation function) and asks, "Is this one actually doing anything?" If a sheet is just repeating zeros or adding nothing new, KANELÉ throws it away.

• Why this is special: In old LUT systems, throwing away a book breaks the whole library because the books are chained together. In KANELÉ, the books are just added together. You can throw one away, and the math still works perfectly. This makes the system incredibly small.

C. The "Assembly Line" (Pipelining)

Even with small cheat sheets, you don't want to wait for the librarian to find the book, read it, and then find the next one.
KANELÉ builds a conveyor belt. While the chip is looking up the answer for step 1, it's already looking up the answer for step 2. This allows the chip to run at lightning speed (over 800 MHz), processing thousands of tasks per second.

3. The Results: A Miracle of Speed and Size

When the authors tested KANELÉ, the results were shocking:

• Speed: It was up to 2,700 times faster than previous attempts to run KANs on chips.
• Size: It used 4,000 times less memory (LUTs) than the old methods.
• Efficiency: It didn't need any expensive "specialized math engines" (DSPs) or big memory banks (BRAM). It ran entirely on the basic logic blocks of the chip, like a car running on regular gas instead of rocket fuel.

4. Real-World Superpowers

The paper didn't just stop at math tests. They showed KANELÉ doing real jobs:

• Physics & Science: It solved complex physics formulas better than standard AI, proving it's great for tasks that follow natural laws.
• Robot Control (The "HalfCheetah"): They taught a simulated robot cheetah to run. The KAN controller was 5 times smaller than a standard AI controller but made the robot run faster and more stably. It's like replacing a heavy, clumsy robot brain with a tiny, super-fast one that fits in a watch.

The Big Takeaway

Think of KANELÉ as the bridge that finally allowed the "cheat sheet" style of AI (KANs) to leave the textbook and enter the real world.

Before, people thought KANs were too heavy for hardware. KANELÉ proved that if you organize them correctly—turning them into simple lookup tables, throwing away the junk, and putting them on a conveyor belt—they become the fastest, smallest, and most energy-efficient AI available for tasks that need real-time answers.

It's the difference between carrying a library in a backpack (old way) and having a magical, instant-access digital menu (KANELÉ).

Technical Summary

1. Problem Statement

Low-latency, resource-efficient neural network inference on Field-Programmable Gate Arrays (FPGAs) is critical for real-time applications in robotics, scientific computing, and edge AI. While Lookup Table (LUT)-based neural networks have emerged as a solution to replace arithmetic-heavy operations with precomputed logic, existing approaches face limitations:

• Inefficiency of Prior KAN Implementations: Kolmogorov–Arnold Networks (KANs), which use learnable spline functions instead of fixed activations, have shown superior accuracy and interpretability in software. However, previous attempts to deploy KANs on FPGAs (e.g., by Tran et al.) relied on expensive spline evaluations using BRAM and DSP blocks, resulting in prohibitive latency and resource usage (making them impractical).
• Pruning Limitations in LUT-NNs: Traditional LUT-based networks (like NeuralLUT or TreeLUT) often rely on sequential indexing where LUTs are chained. This structure makes pruning (removing unused connections) extremely difficult without breaking the model topology.
• Gap in Control Systems: There is a lack of efficient, low-power neural architectures capable of handling continuous control tasks (e.g., reinforcement learning) on resource-constrained hardware.

2. Methodology: The KANELÉ Framework

The authors introduce KANELÉ, a framework that re-formulates KAN inference entirely around FPGA-native LUT primitives, leveraging the Kolmogorov–Arnold Representation Theorem.

Core Architecture

• LUT-Native Activation: Instead of approximating KAN splines with arithmetic, KANELÉ treats each learnable 1D activation function $\phi(x)$ as a direct mapping to a Lookup Table. Since KANs decompose multivariate functions into sums of univariate functions, each edge in the network can be quantized and stored as a compact truth table.
• Additive Independence: Unlike chained LUT networks, KANs compute outputs via summation of independent edge functions. This structure allows for natural pruning: if an edge's contribution is negligible, it can be removed without disrupting the connectivity of other nodes.

Design Flow & Optimization

1. Quantization-Aware Training (QAT): The framework uses AMD's Brevitas library to train KANs with low-bit precision (e.g., 2–8 bits). Quantizers are applied at inputs and layer outputs, with gradients approximated using the Straight-Through Estimator (STE).
2. Norm-Based Pruning: During training, the importance of each spline connection is evaluated using the $L_2$ norm of its activation over the input domain. Connections below a dynamic threshold are pruned, significantly reducing the number of required LUTs.
3. Automated Toolflow: The system automatically converts trained PyTorch KANs into synthesizable VHDL RTL. It generates:
   • Logical-LUTs (L-LUTs): Truth tables representing the quantized spline functions.
   • Pipelined Adder Trees: To handle the summation of multiple LUT outputs, balanced adder trees with pipeline registers are inserted to maximize clock frequency and minimize critical path delays.
   • Synthesis: The output is compiled using Vivado for out-of-context synthesis to isolate core performance metrics.

3. Key Contributions

1. First FPGA-Tailored KAN Architecture: KANELÉ is the first framework to map KANs directly to LUTs, eliminating the need for BRAM and DSP blocks entirely. This shifts the paradigm from "emulating arithmetic" to "direct logic configuration."
2. Co-Optimization of Training and Hardware: The framework integrates pruning and quantization into the training loop, ensuring that the resulting model is hardware-efficient without sacrificing accuracy.
3. Open-Source Toolchain: An automated flow is provided that compiles KANs into FPGA bitstreams in seconds, supporting diverse domains (vision, physics, control).
4. Extension to Control Systems: The framework is successfully extended to real-time reinforcement learning (RL) control tasks, demonstrating viability beyond standard supervised learning.

4. Experimental Results

The authors evaluated KANELÉ across three categories of benchmarks: standard LUT-NN datasets, prior KAN-FPGA benchmarks, and complex MLPerf Tiny tasks.

Performance vs. Prior KAN-FPGA (Tran et al.)

• Resource Savings: KANELÉ achieves a >4000x reduction in LUT usage and >4000x reduction in Flip-Flops compared to the previous KAN FPGA implementation.
  • Example (Dry Bean dataset): KANELÉ uses 402 LUTs vs. 1.6 million LUTs in prior work.
• Latency & Speedup: KANELÉ achieves latencies in the nanosecond range (e.g., 7.1 ns), representing a ~2700x speedup over prior implementations (18,960 ns).
• Frequency: Sustains clock frequencies up to 1736 MHz.

Performance vs. State-of-the-Art LUT-NNs

• JSC CERNBox (Jet Tagging): KANELÉ achieves 75.1% accuracy (matching NeuralLUT) with 18x fewer LUTs and the best Area$\times$Delay product ($4.1 \times 10^4$).
• MNIST: Achieves 96.3% accuracy with 3809 LUTs. While specialized image models (like TreeLUT) have slightly lower latency, KANELÉ offers a superior balance of resources and accuracy, using 20x fewer LUTs than PolyLUT.
• MLPerf Tiny (ToyADMOS): Outperforms hls4ml implementations by 41.7% in LUT usage and 71.4% in FF usage, while delivering 330x higher throughput and 9,840x lower energy per inference.

Control Systems (HalfCheetah RL)

• In a reinforcement learning task, an 8-bit quantized KAN actor (with ~5x fewer parameters than an MLP baseline) achieved a higher reward (2762 vs. 1558).
• Hardware deployment showed the KAN actor consumed <1% of the resources (LUTs/FFs) of the MLP baseline while achieving ~200x lower latency (4.5 ns vs. 893 ns).

5. Significance and Impact

• Paradigm Shift: KANELÉ proves that KANs are not inherently hardware-inefficient; rather, their previous inefficiency stemmed from using arithmetic-based implementations. By aligning the "activation-centric" KAN structure with the "logic-centric" nature of FPGAs, the framework unlocks extreme efficiency.
• Scalability: The ability to prune KANs naturally makes them ideal for resource-constrained environments where model size must be minimized without retraining.
• Real-Time Control: The success in the HalfCheetah benchmark demonstrates that KANs are viable for safety-critical, low-latency control systems (e.g., robotics, plasma stabilization, quantum error correction) where traditional MLPs are too heavy or slow.
• Interpretability + Efficiency: KANELÉ retains the interpretability benefits of KANs (learnable functions) while solving the hardware deployment bottleneck, bridging the gap between scientific computing and embedded AI.

In conclusion, KANELÉ establishes a new state-of-the-art for FPGA neural inference, offering a highly efficient, low-latency, and resource-sparing alternative to both traditional MLPs and existing LUT-based networks, particularly for tasks involving symbolic or physical relationships.