NL2GDS: LLM-aided interface for Open Source Chip Design

NL2GDS is a novel framework that leverages large language models to automatically translate natural language hardware specifications into synthesizable RTL and complete GDSII layouts via the OpenLane flow, achieving significant improvements in area, delay, and power efficiency while democratizing ASIC design.

The Gist

Imagine you want to build a custom house. In the past, you had to be an expert architect, a structural engineer, and a master builder all at once. You'd need to draw blueprints, calculate load-bearing walls, and write thousands of lines of code to tell the construction robots exactly where to put every brick. If you made a tiny mistake, the whole house could collapse, and you'd have to start over.

NL2GDS is like hiring a super-smart, magical construction foreman who speaks your language. You don't need to know how to draw blueprints or write code. You just tell him, "I need a house with three bedrooms, a big kitchen, and a solar roof," and he handles the rest.

Here is a simple breakdown of how this "magical" system works, using everyday analogies:

1. The Problem: The "Language Barrier"

Currently, designing computer chips (the brains of our phones and computers) is incredibly difficult. It requires a specialized language called "RTL" (Register-Transfer Level), which is like a complex programming language only experts speak. There is a huge gap between your idea ("I want a fast calculator") and the final physical chip you can hold in your hand. Most people can't cross this gap because it's too expensive and technical.

2. The Solution: The "Magic Translator" (NL2GDS)

The authors created a tool called NL2GDS (Natural Language to GDSII). Think of it as a universal translator that turns your plain English sentences directly into a finished, factory-ready chip design.

• You speak: "Make me a traffic light controller that turns green for 30 seconds."
• The AI thinks: It breaks this down, figures out the logic, and writes the code.
• The AI builds: It doesn't just stop at code; it actually designs the physical layout of the chip, ready to be printed by a factory.

3. How It Works: The "Dream Team" of Robots

Instead of one robot trying to do everything (which often leads to mistakes), NL2GDS uses a team of specialized AI agents, like a construction crew:

• The Architect (The Planner): This agent listens to your idea and asks clarifying questions. "Do you want the traffic light to be fast or save energy?" It creates a detailed plan.
• The Builder (The Code Generator): This agent writes the actual instructions (the Verilog code) for the chip. If it makes a mistake, it checks its own work and fixes it before moving on.
• The Inspector (The Quality Control): This agent looks at the blueprint and says, "Hey, this wall is too thin," or "This room is too small." It uses a special library (called RAG) to look up the rules of chip building and suggests fixes.
• The Foreman (The Orchestrator): This agent runs the whole show. It tells the other robots what to do, runs the construction in the cloud, and speeds things up by having multiple robots work at the same time.

4. The "Self-Correction" Superpower

One of the coolest parts is how the system learns from its mistakes. Imagine you are baking a cake, and the oven says, "Too hot!"

• Old way: You throw the cake away and try again, hoping you guessed the right temperature.
• NL2GDS way: The AI reads the "oven error," looks up a cookbook of successful cakes, adjusts the temperature, and bakes a better cake automatically. It keeps doing this until the chip is perfect, without you needing to lift a finger.

5. The Results: Faster, Cheaper, and Better

The researchers tested this system on standard "test circuits" (like math problems for chips). The results were surprising:

• Smaller Chips: The AI-designed chips were up to 36% smaller than the ones designed by humans using traditional methods. It's like fitting a whole mansion into a studio apartment.
• Faster Chips: They were up to 35% faster.
• Energy Saving: They used up to 70% less power. This is huge for battery-powered devices like smartwatches or IoT sensors.

6. Why This Matters: Democratizing the Future

Before this, only giant companies like Intel or Apple could afford to design their own chips because it cost millions of dollars and took years.
NL2GDS is like giving everyone a 3D printer for computer chips.

• A student in a classroom can design a chip for a science project.
• A startup can prototype a new idea in an hour instead of a year.
• The cost drops from thousands of dollars to just a few cents in cloud computing fees.

The Bottom Line

This paper introduces a tool that turns "I have an idea" into "I have a working chip." It removes the need for years of specialized training, allowing anyone with a natural language description to create high-performance hardware. It's not just about making chips easier; it's about unlocking a new wave of innovation where the only limit is your imagination, not your ability to write code.

Technical Summary

Here is a detailed technical summary of the paper "NL2GDS: LLM-Aided Interface for Open Source Chip Design."

1. Problem Statement

The field of hardware design faces a significant bottleneck due to the widening gap between high-level specifications and Register-Transfer Level (RTL) implementation. Traditional ASIC design workflows are complex, multi-stage processes (spanning RTL design, synthesis, floorplanning, placement, routing, and verification) that rely on expensive, proprietary Electronic Design Automation (EDA) tools. This creates high barriers to entry for Small and Medium-sized Enterprises (SMEs) and educational institutions.

While recent advancements in Large Language Models (LLMs) have enabled natural language programming in software, existing hardware design tools using LLMs are limited. Most current approaches only generate RTL code or act as "copilots" for specific tasks, failing to bridge the gap to manufacturable physical layouts (GDSII). Furthermore, existing systems lack the ability to incorporate backend physical design feedback (timing, power, area) into the generative loop, preventing true end-to-end automation from natural language to a foundry-ready chip layout.

2. Methodology: The NL2GDS Framework

The authors propose NL2GDS, a novel framework that translates natural language hardware descriptions directly into synthesizable RTL and complete GDSII layouts using the open-source OpenLane ASIC flow. The system is built on a modular, AI-driven pipeline consisting of four core components:

A. System Architecture

• Web-Based Front End: A browser-based interface (built with Streamlit) that integrates with KLayout and OpenRoad GUIs, eliminating the need for Command Line Interface (CLI) scripting and lowering the knowledge barrier for users.
• Agentic Approach: Instead of a single LLM call, the system employs a team of specialized agents. These agents orchestrate the flow, interact with OpenLane, and utilize Retrieval-Augmented Generation (RAG) to access project-specific documentation and successful design examples.
• Chain of Thought (CoT): The system decomposes complex design tasks into smaller subtasks (planning, Verilog generation, verification, error correction, optimization). An optimized planning agent collaborates with the user to clarify intent before generating code.
• Cloud Backend: The entire flow runs in the cloud, leveraging parallel processing to handle resource-intensive tasks like parameter sweeps and layout optimization without requiring local high-performance computing resources.

B. Key Technical Mechanisms

1. RAG for Configuration: Since LLMs lack inherent knowledge of the ~800 design parameters controlling OpenLane, the system uses RAG to inject relevant documentation, parameter guides, and successful design examples into the prompt. This allows the LLM to generate valid configuration files and fix errors based on specific OpenLane logs.
2. Iterative Refinement Loop:
   • Generation: The LLM generates Verilog code.
   • Verification: A separate agent and automated tools (e.g., Verilator in lint mode) check for syntax errors, compatibility issues, and logic flaws.
   • Backend Feedback: Once the code passes verification, it enters the OpenLane flow. The system extracts metrics (timing slack, area utilization, DRC violations) and feeds them back to the LLM.
   • Optimization: The LLM uses these metrics to iteratively refine the RTL and adjust OpenLane configuration parameters to meet Power, Performance, and Area (PPA) goals.
3. Parallel Execution: To overcome Python's Global Interpreter Lock (GIL) limitations, the system decouples OpenLane execution from the Python runtime. It launches multiple OpenLane runs as independent subprocesses on multicore servers, achieving significant speedups in design exploration.

3. Key Contributions

1. First End-to-End NL-to-GDS Pipeline: NL2GDS is the first framework to translate natural language specifications directly into manufacturable GDSII layouts using an open-source flow, moving beyond simple RTL generation.
2. Backend-Aware Generative Loop: Unlike prior work, this system integrates physical design feedback (timing, routing, DRC) into the generative process, allowing the LLM to optimize designs based on real-world silicon constraints.
3. Modular Multi-Agent Architecture: The use of specialized agents with RAG and CoT reasoning significantly improves the reliability of HDL generation and error correction compared to single-shot LLM prompts.
4. Democratization of Chip Design: By abstracting low-level implementation details and running in the cloud, the system enables users with limited EDA expertise to produce foundry-ready designs.

4. Experimental Results

The system was evaluated using ISCAS'85 and ISCAS'89 benchmark designs (e.g., ALUs, multipliers, traffic light controllers) implemented with the Skywater 130nm PDK.

• Code Generation Accuracy: When tested on the VerilogEval dataset (specifically complex FSM tasks), integrating NL2GDS with CoT improved the testbench pass rate dramatically. For example, with Gemini 2.5 Pro, the pass rate increased from 3.79% (baseline) to 83.70%. With GPT-5, it reached 100%.
• PPA Improvements: Compared to baseline ISCAS designs (which are already highly optimized gate-level implementations), NL2GDS achieved:
  • Area Reduction: Up to 54.71% (e.g., 16x16 Multiplier) and an average of 36% across benchmarks.
  • Delay Reduction: Up to 35.29% (e.g., 16x16 Pipelined Multiplier) and an average of 35%.
  • Power Savings: Up to 69.55% (e.g., 16-bit error detector) and an average of 70%.
• Efficiency: The system demonstrated rapid prototyping capabilities. A complete design cycle for a 16x16 multiplier (including 98 optimization runs) took only one hour and cost approximately $1.12 in LLM and cloud compute fees.
• Parallelism: The parallel implementation reduced the average runtime per flow from 132 seconds (sequential) to 37.5 seconds, a 3.46x speedup.

5. Significance

NL2GDS represents a transformative step in Electronic Design Automation (EDA). By successfully bridging the gap between natural language intent and physical silicon layout, it:

• Accelerates Innovation: Drastically reduces the time-to-layout, enabling rapid prototyping and iteration of hardware architectures.
• Lowers Barriers: Makes ASIC design accessible to researchers, educators, and SMEs who lack expensive proprietary tools or deep EDA expertise.
• Validates Generative AI in Hardware: Proves that LLMs, when coupled with RAG and iterative physical design feedback, can not only write code but also optimize complex hardware designs to compete with or exceed human-engineered benchmarks.

The framework suggests a future where hardware design is as accessible as software development, potentially revolutionizing the development of edge-AI and IoT devices where efficiency and speed are critical.