Development of Readout Electronics for a High-Speed Event-Driven Neutron Imaging Detector Based on Timepix4

This paper presents the development of a compact, high-performance readout electronics system based on the Timepix4 chip and a single ZYNQ-MPSOC, designed to meet the high event-rate demands of the Phase II Chinese Spallation Neutron Source by achieving stable 5.12 Gbps data transmission and demonstrating successful X-ray imaging capabilities.

The Gist

Here is an explanation of the paper, translated into everyday language with some creative analogies.

The Big Picture: Catching the "Neutron Rain"

Imagine the China Spallation Neutron Source (CSNS) as a massive, high-powered sprinkler system shooting out pulses of invisible particles called neutrons. These neutrons are like tiny, ghostly raindrops that can pass through solid objects to reveal their hidden internal structures (like seeing the bones inside a fish without cutting it open).

As the facility upgrades to "Phase II," this sprinkler is going to turn up the pressure. The "rain" of neutrons will become much heavier and faster. The current cameras (detectors) used to catch these neutrons are like old, slow film cameras; they can't keep up with the deluge. They would get overwhelmed, missing data or getting blurry.

The Solution: The team built a brand-new, super-fast digital camera system based on a chip called Timepix4. Think of this new system as a high-speed, professional sports camera capable of capturing every single drop of that heavy neutron rain, even when it's pouring down.

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1. The Hardware: A Compact Powerhouse

The team needed to build the "brain" and "wiring" for this new camera, but they had a tricky constraint: space. The detector is squeezed into a tight spot, so the electronics had to fit into a box no bigger than a large pizza box (8 cm × 30 cm).

• The Two-Part System: They split the electronics into two boards connected by a custom plug (like a high-speed USB-C cable):

  1. The Sensor Board: This holds the Timepix4 chip. It's the "eye" of the camera. It has a special cooling system (a tiny refrigerator) to keep the sensor cool, ensuring it doesn't get "sweaty" and make mistakes.
  2. The Digital Brain: This is a powerful computer chip (ZYNQ-MPSOC) that acts as the manager. It controls the sensor, gathers the data, and sends it away.

• The Super-Highway: The biggest challenge was moving data. The sensor generates a massive amount of information. To handle this, they built 16 super-fast lanes (data channels) to carry the data out.

  • Analogy: Imagine a highway with 16 lanes. Currently, they are driving at 5.12 Gbps (a very fast speed). The highway is designed to eventually handle 10.24 Gbps per lane, which would be like turning those lanes into 16-lane super-expressways.

2. The Software: The Traffic Controller

Having a fast highway is useless if the traffic jams at the exit. The team wrote special software (firmware) to act as a traffic controller.

• The Rush Hour Problem: Neutron beams come in bursts (pulses). Imagine a sudden wave of cars hitting the highway all at once.
• The Buffer Strategy: The system uses a clever two-step storage plan:
  1. Fast Memory (FIFO): Like a small waiting room right at the entrance, this holds data for split seconds.
  2. Big Memory (SODIMM): If the "rush hour" gets too crazy and the waiting room fills up, the system dumps the extra cars into a massive parking garage (32 GB of external memory).
• The Exit: Once the wave of neutrons passes and the traffic slows down, the system calmly drives all the stored data out through a single, high-speed fiber optic cable (40 Gbps) to a computer for analysis.

3. The Testing: Proving It Works

Before they can use this on real neutrons, they had to prove it works.

• The "Eye" Test: They sent test signals through the 16 data lanes.

  • Result: At the current speed (5.12 Gbps), the signal was crystal clear—no errors at all. It's like driving on a perfectly smooth road with no potholes.
  • The Challenge: When they tried to push the speed to the maximum (10.24 Gbps), the signal got a bit "jittery" (the road got bumpy). They are still investigating why, but for now, the current speed is plenty fast for the job.

• Calibrating the Sensors (Equalization):

  • The Problem: When you buy a new camera, sometimes one pixel is slightly too sensitive and another is too dull. In this chip, the "sensitivity" of the millions of tiny pixels varied wildly (like a choir where everyone is singing a different note).
  • The Fix: They ran a "tuning" process. They adjusted the volume knob for every single pixel until they all sang the same note.
  • Result: The variation dropped from a huge mess to almost perfect uniformity.

• The Fish Test:
  To prove the whole system works together, they took an X-ray picture of a small fish.

  • The Result: The image was incredibly sharp. You could clearly see the fish's bones. This proved that the electronics could capture data accurately, process it without losing information, and produce a clear picture.

Conclusion: Ready for the Real Deal

In short, the team has successfully built a compact, high-speed, and reliable readout system for the next generation of neutron imaging.

• Status: The hardware is built, the software is written, and the "fish test" was a success.
• Next Step: They plan to install this system on the actual neutron detector. Once there, it will be ready to handle the intense "neutron rain" of the upgraded CSNS facility, helping scientists see the invisible world inside materials with unprecedented clarity.

The Takeaway: They took a complex, high-speed problem and solved it by building a compact, efficient system that acts like a super-fast traffic manager, ensuring not a single drop of data is lost in the storm.

Technical Summary

Here is a detailed technical summary of the paper "Development of Readout Electronics for a High-Speed Event-Driven Neutron Imaging Detector Based on Timepix4."

1. Problem Statement

The Chinese Spallation Neutron Source (CSNS) is entering Phase II, which involves a significant increase in proton beam power. This upgrade leads to a substantial boost in the intensity of pulsed neutron beams, creating a critical demand for higher event-rate readout electronics for energy-resolved neutron imaging detectors.

Existing solutions present limitations:

• Current Detectors: The existing CSNS detector relies on optical event cameras (TPX3Cam) which may not scale sufficiently for the increased flux.
• Commercial Systems: The SPIDR4 system (developed by NIKHEF for Timepix4) allows for control and testing but requires additional hardware to achieve full-bandwidth readout and is not fully compatible with the existing CSNS detector infrastructure.
• Requirements: The new system must support a massive event rate (up to 2.5 Ghits/s), provide full 160 Gbps bandwidth for a single Timepix4 chip, fit within a compact form factor (8 cm × 30 cm), and integrate seamlessly with the detector's optical and shielding constraints.

2. Methodology

The authors developed a dedicated, high-performance readout electronics system based on the Timepix4 hybrid pixel detector ASIC. The solution is divided into hardware design, firmware architecture, and system testing.

A. Hardware Design

The system is compact (8 cm × 30 cm) and radiation-hardening is deemed unnecessary because the electronics are shielded and only detect visible light reflected from the scintillator.

• Architecture: The system is split into two boards connected via a custom FMC interface:
  1. Timepix4 Chip Board: Provides power (using DC-DC converters and LDOs), clock signals (SI5345A), and thermal management. It includes a Thermoelectric Cooler (TEC) to maintain stable sensor temperature, minimizing leakage current and noise.
  2. Digital Readout Board: The core is a ZYNQ-MPSOC (XCZU15EG) containing an ARM CPU (running Linux for control) and an FPGA.
     • Data In: 16 pairs of GTH transceivers receive data from Timepix4 via the FMC connector.
     • Data Out: A high-capacity SODIMM DDR4 memory interface (up to 32 GB) acts as a buffer for high-bandwidth data.
     • Output: Data is transmitted via a single 40 Gbps QSFP+ interface.

B. Firmware Design

The firmware manages data flow, synchronization, and reliability:

• Protocols: Control commands use TCP (via the PS) for reliability, while experimental data uses UDP for high-bandwidth efficiency.
• Data Processing:
  • Data from the 16 Timepix4 channels is formatted into AXI-Stream protocol.
  • Data enters asynchronous FIFOs, then is merged via 8-channel AXI-Stream buses managed by a Buffer Control module.
• Buffering Strategy: To handle the pulsed nature of the neutron beam (25 Hz, peak flux up to $10^7$ n/s/cm²), the system employs a multi-tiered caching architecture. If the input bandwidth exceeds the 40 Gbps real-time transmission limit, excess data is temporarily stored in the external SODIMM memory and retrieved during idle periods.

C. Testing Methodology

• Link Integrity: Long-duration PRBS-31 tests were conducted on the Gigabit Wireline Transmitter (GWT) links using Vivado IBERT.
• Sensor Calibration: Pixel threshold equalization was performed to correct manufacturing variations.
• Functional Validation: X-ray imaging experiments were conducted using a Hamamatsu X-ray source and a 300 $\mu$m silicon sensor to verify the system's ability to capture structural details.

3. Key Contributions

• Custom High-Speed Interface: Development of a custom FMC interface and firmware capable of handling 16 data channels simultaneously.
• Compact, Single-Chip Solution: Achieved full system functionality (control, processing, buffering, transmission) on a single ZYNQ-MPSOC chip within a highly constrained physical footprint.
• High-Capacity Buffering: Implementation of a 32 GB SODIMM interface to manage bursty data traffic from pulsed neutron sources, ensuring no data loss during peak flux.
• Thermal Management Integration: Direct integration of a TEC beneath the PCB to actively cool the Timepix4 sensor, a critical factor for low-noise operation in high-flux environments.

4. Results

• Data Link Performance:
  • Successfully established 16 error-free data channels operating at 5.12 Gbps (half the theoretical max of 10.24 Gbps).
  • Bit Error Rate (BER) was consistently below $10^{-14}$ at 5.12 Gbps.
  • Links were also tested at 10.24 Gbps, achieving BERs between $10^{-5}$and$10^{-8}$, though the eye diagram showed reduced opening, likely due to wire-bonding parasitic effects.
• Sensor Equalization:
  • Initial pixel threshold standard deviation was ~500 $e^-$.
  • After equalization using 32 local DAC codes per pixel, the standard deviation was reduced to < 50 $e^-$.
  • Only 3 pixels required masking (outliers).
• Imaging Validation:
  • X-ray experiments successfully imaged a small fish sample.
  • The resulting images clearly resolved bone structures, confirming the system's functionality and the uniformity of the sensor response after equalization.

5. Significance

This work represents a critical step toward upgrading the CSNS detector capabilities for Phase II operations. By developing a custom, high-bandwidth readout system tailored specifically for the Timepix4 chip, the authors have:

1. Solved the Bandwidth Bottleneck: The system supports the high event rates required for next-generation neutron imaging, capable of handling the increased flux from the upgraded spallation source.
2. Ensured Compatibility: The system is designed to integrate directly with existing detector infrastructure, overcoming the limitations of generic commercial readout systems.
3. Validated Performance: Preliminary results confirm that the electronics can achieve the necessary speed, stability, and image quality.
4. Future Outlook: The system is planned for installation on the energy-resolved neutron imaging detector, paving the way for advanced non-destructive testing and stress distribution analysis in materials science.