Reliable and High Performance IGZO and In2O3 Transistors via Channel Capping

This paper demonstrates a reliable, high-performance strategy for IGZO and In2O3 transistors compatible with a 400°C BEOL thermal budget, featuring a novel amorphous In2O3/SiO2 capping layer that achieves a high mobility of 33.1 cm²/V·s and minimal threshold voltage shift under stress.

The Gist

Imagine you are building a high-speed highway for tiny electronic signals. The "cars" on this highway are electrons, and the "road" they travel on is made of special materials called IGZO and Indium Oxide (InO). These materials are amazing because they let electrons zoom along very fast, which is perfect for making our future electronics (like flexible screens or super-fast processors) work better.

However, there's a big problem: The road is fragile.

The Problem: The "Thin Road" Dilemma

Think of the electronic channel as a road.

• If the road is thin: The cars (electrons) can move very fast and efficiently. This is great for performance. But, the road is so thin that it's easily damaged by traffic jams (heat and electrical stress). It gets "potholed" quickly, causing the system to become unreliable.
• If the road is thick: It's very sturdy and reliable. But now the cars have to drive through a deep tunnel, which slows them down significantly.

For years, engineers had to choose: Speed OR Reliability. You couldn't have both. If you tried to fix the reliability of a thin road by adding "patches" (doping), the road would get so clogged that the cars slowed down to a crawl.

The Solution: The "Smart Cover" Strategy

The researchers at IBM came up with a clever trick to solve this. Instead of making the road itself thicker (which slows things down), they kept the road thin for speed but built a super-strong, invisible shield over the top of it.

Here is how they did it, broken down into two parts:

1. The IGZO Solution: The "Double-Layer" Road

For the IGZO material, they realized they could separate the "driving lane" from the "protective layer."

• The Idea: Imagine a thin, high-speed race track (the channel). Usually, if you put a heavy blanket over it to protect it, the cars get stuck.
• The Innovation: They built a special structure where the "race track" is thin (for speed), but they added a thick, extra layer of the same material on top of the track, acting like a protective roof.
• The Result: The cars still drive on the thin, fast lane, but the thick roof above them absorbs all the damage and stress. The road stays fast, but it becomes as tough as a thick road.

2. The InO Solution: The "Magic Invisible Wall"

Indium Oxide (InO) is even faster but even more temperamental. It has a nasty habit: if you try to put a standard protective cover on it, the cover and the road start to mix (like oil and water that refuse to separate), creating a "short circuit" where the cars take a wrong turn and the system fails.

• The Problem: Standard covers (like glass or silicon dioxide) cause the road to crystallize (turn into a brittle crystal) or mix with the cover, ruining the speed.
• The Innovation: They created a new type of "magic cover" made by mixing Indium Oxide with a tiny bit of Silicon Dioxide (SiO₂).
  • Think of this like adding a special "stabilizer" to a liquid.
  • This new mixture (InO-SiO) stays soft and amorphous (like glass) even when it's thick, so it doesn't crack.
  • Crucially, it acts as an insulator (a wall that stops electricity) rather than a conductor. This prevents the "mixing" problem.
• The Result: They used this magic mixture as both the protective roof and a virtual extension of the road.
  • The result? A transistor that is super fast (33.1 cm²/Vs, which is very high!) and super stable.
  • When they stressed the device (threw a lot of traffic at it), the "magic cover" held up perfectly, with almost no shift in performance.

Why This Matters

In the past, engineers had to compromise. They had to make devices slower to make them last longer, or make them fast but fragile.

This paper shows a way to have your cake and eat it too. By using these "smart covers" and understanding the physics of how the materials behave, they created transistors that:

1. Zoom: They are incredibly fast (high mobility).
2. Endure: They can handle heat and electrical stress without breaking down.
3. Fit: They can be made small enough to fit into the tiny spaces of future chips.

The Takeaway

Imagine you have a super-fast sports car. Usually, if you drive it on a rough track, it breaks. If you put it in a garage, it's safe but you can't drive it.
These researchers built a reinforced, transparent garage roof that lets the car drive at top speed while protecting it from the elements. They didn't just patch the car; they redesigned the environment around it so the car can perform its best without fear.

This is a huge step forward for making the next generation of electronics that are both lightning-fast and incredibly durable.

Technical Summary

1. Problem Statement

Indium Gallium Zinc Oxide (IGZO) and Indium Oxide (InO) are promising materials for Back-End-of-Line (BEOL) active devices due to their compatibility with thermal budgets (up to 400°C) and high mobility (especially InO). However, they face a fundamental trade-off between performance and reliability:

• Thickness Dilemma: Thin channels are required for high ON-current and low access resistance, but they suffer from poor bias stress stability (Positive/Negative Bias Stress, PBS/NBS) and high hysteresis. Thick channels offer better reliability but degrade performance and, in the case of InO, tend to crystallize, increasing variability.
• Stability Issues: Conventional strategies like elemental doping or alloying often degrade mobility significantly before achieving acceptable reliability.
• Encapsulation Challenges: Standard SiO₂ encapsulation often fails to prevent performance degradation or, in the case of InO capped with other oxides (like IGZO), can create conductive shunt paths due to interdiffusion at the interface.

2. Methodology and Device Strategy

The authors propose a material-driven strategy that exploits intrinsic oxide properties to decouple channel thickness requirements for performance versus reliability. The study utilizes:

• Fabrication: Shadow-mask-based fabrication to eliminate lithographic defects and ensure precise layer alignment.
• Process: Sputtering deposition of channel, source/drain (SD), capping, and encapsulation layers, followed by a 400°C anneal to meet BEOL thermal budget constraints.
• Innovative Structures:
  1. IGZO: A "virtual channel" structure where a thicker oxide semiconductor layer is added on top of the thin active channel before encapsulation. This separates the thin contact region (for performance) from the thicker bulk region (for reliability).
  2. InO: Development of an InO–SiO (Indium Oxide doped with SiO₂) capping layer. By doping InO with >25% SiO₂, the material transitions into an amorphous insulating phase. This layer serves a dual purpose: it acts as a virtual channel (preventing crystallization of the underlying thick InO) and as an encapsulation layer (passivating the surface).

3. Key Contributions

• Decoupling Thickness Constraints: The paper demonstrates a device architecture where the contact region remains thin for high mobility, while the channel bulk is thickened (via capping) to enhance reliability without sacrificing performance.
• InO–SiO Material Innovation: The discovery that SiO₂-doped InO (>25% SiO₂) forms an amorphous insulator that is compatible with InO processing. This prevents the crystallization of thick InO films and eliminates the conductive shunt paths observed when capping InO with other semiconducting oxides (like IGZO).
• High-K Dielectric Integration: The study highlights the critical role of high-k gate dielectrics (e.g., HfO₂) in suppressing threshold voltage ($V_t$) shifts via the relationship $\Delta V_t = \Delta Q / C_{ox}$, where higher gate capacitance ($C_{ox}$) reduces the impact of interface charge trapping.

4. Experimental Results

IGZO Transistors

• Performance: An innovative IGZO transistor with a 10 nm channel contact and a 50 nm IGZO capping layer achieved an extrinsic saturation mobility of 22 cm²V⁻¹s⁻¹.
• Reliability: The device exhibited near-zero hysteresis and a minimal Positive Bias Stress (PBS) shift of 15 mV (even with 50 nm SiO₂ gate dielectrics).
• Mechanism: The thick capping layer improved surface passivation and reduced the impact of surface defect states, while the thin contact region maintained low access resistance.

InO Transistors

• Mobility: A 3.5 nm InO channel with an InO–SiO capping layer on a 10 nm HfO₂ gate dielectric achieved a saturation mobility of 33.1 cm²V⁻¹s⁻¹. This is comparable to (and slightly better than) uncapped InO devices (34.5 cm²V⁻¹s⁻¹) and significantly superior to devices with conventional SiO₂ encapsulation (19 cm²V⁻¹s⁻¹).
• Stability: The InO–SiO capped device showed a positive $V_t$ and an exceptionally low PBS shift of only 5 mV after 1000 seconds at 3 MV/cm.
• Material Properties: The InO–SiO capping layer effectively prevented the crystallization of the underlying InO and acted as a high-quality insulator, unlike standard oxide caps which caused interdiffusion and shunt conduction.

General Observations

• Thickness Dependence: Thinner channels consistently showed worse PBS stability and higher hysteresis.
• Passivation Impact: Top surface passivation significantly improved PBS/NBS behavior for both materials.
• Short-Channel Scalability: TCAD simulations confirmed that the innovative structure (thick capping over thin channel) works effectively for short-channel devices (e.g., 100 nm gate length), allowing the bottom gate to fully shut off the channel despite the extra capping layer.

5. Significance

This work provides a robust solution to the long-standing performance-reliability trade-off in oxide electronics. By introducing the InO–SiO capping strategy and the dual-thickness channel architecture, the authors demonstrate that it is possible to achieve:

1. High Mobility: Retaining the intrinsic high-speed capabilities of InO and IGZO.
2. Superior Reliability: Achieving minimal threshold voltage shifts under stress, surpassing conventional encapsulation methods.
3. BEOL Compatibility: The process is fully compatible with standard 400°C thermal budgets and scalable to short-channel devices.

These findings are critical for the integration of high-performance oxide transistors into advanced logic and memory circuits, particularly for applications requiring high-speed operation and long-term stability.