Automatic Charge State Tuning of 300 mm FDSOI Quantum Dots Using Neural Network Segmentation of Charge Stability Diagram

This paper presents a deep learning-based pipeline using a U-Net CNN to automatically tune 300 mm FDSOI quantum dots by segmenting charge stability diagrams, achieving an 80% success rate in locating the single-charge regime and offering a scalable path toward high-throughput qubit automation.

The Gist

Imagine you are trying to build a massive library of tiny, super-fast computers called quantum computers. To make these work, you need to arrange billions of microscopic "switches" (called qubits) with perfect precision.

In the world of silicon-based quantum computers, these switches are made by trapping single electrons in tiny cages called Quantum Dots. But here's the problem: making these cages is like trying to bake a perfect cake in a kitchen where the oven temperature changes randomly, and the flour is slightly different in every batch.

The Problem: The "Tuning" Nightmare

To get an electron to sit perfectly in one of these cages, scientists have to adjust several "knobs" (voltage gates) on the device. They do this by looking at a map called a Charge Stability Diagram.

Think of this map like a weather radar.

• The Lines: The dark lines on the radar show where the electron can exist.
• The Goal: You need to find a tiny, specific "safe zone" (the single-electron regime) between two lines where the electron is happy and stable.
• The Old Way: Currently, a human expert has to stare at this radar, guess where the lines are, and manually turn the knobs. If the radar is blurry, noisy, or looks weird (which happens often because of manufacturing flaws), the human has to start over. If you have 1,000 devices to tune, this manual process takes forever and is prone to human error. It's like trying to find a specific needle in a haystack while wearing foggy glasses.

The Solution: The "AI Detective"

This paper introduces a new way to do this using Artificial Intelligence (AI), specifically a type of deep learning called a Neural Network.

Here is how their system works, using a simple analogy:

1. The Training Phase (Teaching the AI)

The researchers gathered a massive library of 1,015 of these "weather radar" maps. These maps came from many different factories, different designs, and different batches of silicon.

• The Human Teachers: Experts manually drew lines on these maps to show the AI exactly where the "safe zones" were. They did this over and over again, creating a huge textbook for the AI to study.
• The Student: They built a smart AI model (based on a U-Net architecture with a MobileNet brain). Think of this AI as a detective who is really good at spotting patterns, even in messy, blurry photos.

2. The Inference Phase (The AI at Work)

Now, when a new device is measured:

1. The Snapshot: The machine takes a picture of the "weather radar" (the stability diagram).
2. The Scan: The AI looks at the entire picture at once (unlike older methods that looked at tiny, isolated patches). It scans the whole map to find the lines.
3. The Prediction: The AI draws a digital mask over the lines it sees, saying, "Here is the first line, and here is the second line."
4. The Target: It calculates the exact center point between those two lines and tells the machine, "Turn the knobs to these specific numbers."

Why This is a Big Deal

The paper reports that this AI system works 80% of the time automatically, even on messy, noisy, or defective devices. For the best designs, it works 88% of the time.

The Analogy of Success:
Imagine you are trying to find a parking spot in a chaotic, crowded city.

• The Old Way: You drive around, squinting, asking people for directions, and guessing. You might get stuck in traffic or hit a car.
• The New Way: You have a self-driving car with a super-vision system. It looks at the whole city map, ignores the noise (other cars, street signs), instantly spots the empty spot, and drives you right into it.

The "Bonus" Feature: Physics Detective

The paper also mentions a cool side effect. Because the AI looks at the whole picture, it doesn't just find the parking spot; it can also tell you why the map looks the way it does.

• It can measure the angle of the lines or the distance between them.
• This gives engineers feedback on how well their factory is working. If the lines are wobbly, the factory knows to fix the silicon manufacturing process. It turns the tuning process into a quality control tool.

The Bottom Line

This research is a major step toward making quantum computers scalable. Instead of needing a team of experts to manually tune thousands of devices (which is impossible for mass production), we can now use an AI "autopilot" to tune them quickly and reliably.

It's the difference between hand-crafting every single part of a car and having a robotic assembly line that can build them perfectly, even if the raw materials aren't 100% identical. This brings us one step closer to having real, usable quantum computers in the future.

Technical Summary

1. Problem Statement

The scaling of spin-qubit technologies, particularly those based on gate-defined semiconductor quantum dots (QDs) in silicon, is hindered by the manual and time-consuming process of charge tuning.

• The Bottleneck: Tuning a QD to the "single-charge regime" (trapping exactly one electron or hole) requires experts to manually interpret Charge Stability Diagrams (CSDs). These are 2D maps of current vs. gate voltages showing Coulomb blockade transition lines.
• Challenges:
  • Complexity: As device arrays grow, the parameter space becomes too large for manual heuristic-based tuning.
  • Variability: Fabrication imperfections (across wafers, batches, and designs) cause significant device-to-device variability, rendering simple, hard-coded scripts ineffective.
  • Limitations of Prior Automation: Previous machine learning (ML) approaches used patch-based methods, where algorithms iteratively scan small sub-regions of a CSD. While faster in data acquisition, these methods lack global context, making them sensitive to noise, discontinuities, and unable to provide holistic device characterization or feedback to fabrication teams.

2. Methodology

The authors propose a Deep Learning (DL) driven, wide-diagram semantic segmentation pipeline that processes full CSDs in a single inference pass.

A. Dataset Construction

• Scale & Diversity: A large, heterogeneous dataset of 1,015 experimental CSDs was assembled.
• Sources: Measured from silicon QD devices on 300 mm wafers using industrial-grade, CMOS-compatible processes at CEA-Leti.
• Variability: The dataset spans nine distinct device designs, two mask layouts, four process batches, seven wafers, and both n-type and p-type polarities.
• Annotation: Ground-truth masks were created by manually tracing transition lines. To ensure quality, a multi-annotator protocol was used where every diagram was labeled by one expert and verified by a second, with consensus reviews for ambiguous cases.

B. Model Architecture

• Framework: A U-Net style Convolutional Neural Network (CNN).
• Encoder: Utilizes MobileNetV2 (pre-trained on ImageNet) as a lightweight encoder. This choice balances accuracy with computational efficiency, featuring depthwise separable convolutions and inverted residuals, making it suitable for deployment on resource-constrained hardware (e.g., cryogenic probes).
• Decoder: A custom decoder with four upsampling stages and skip connections to recover spatial resolution.
• Training Strategy:
  • Loss Function: Dice Loss was used to handle the class imbalance between thin transition lines and the large background.
  • Validation: Five-fold group cross-validation was employed. Crucially, the grouping key was the physical device (design, die, wafer), ensuring that data from the same device never appeared in both training and test sets. This prevents data leakage and ensures the model learns to generalize across fabrication variability rather than memorizing specific device patterns.

C. Inference and Post-Processing

The pipeline converts the raw CSD image into gate-voltage targets through a deterministic post-processing chain:

1. Segmentation: The model outputs a per-pixel probability map of transition lines.
2. Thresholding: Binarization at $\tau = 0.75$.
3. Morphological Closing: Connects fragmented line segments (specifically vertical transitions) using a structuring element.
4. Filtering: Dynamic area filtering removes small, spurious noise artifacts.
5. Extraction: The algorithm identifies the first two transition lines (defining the single-charge regime) based on device polarity (leftmost for n-type, rightmost for p-type).
6. Target Calculation: The centroid of the region between these lines is calculated and mapped back to physical gate voltages ($V_{QD}, V_{SET}$).

3. Key Contributions

1. Wide-Diagram Semantic Segmentation: Unlike previous patch-based approaches, this method processes the entire CSD simultaneously. This provides global context, improving robustness against noise and allowing the detection of any charge regime without iterative exploration.
2. Scalable Dataset & Benchmarking: The creation and validation on a massive, diverse dataset (1,015 CSDs) covering industrial 300 mm wafer variations sets a new benchmark for robustness in quantum device tuning.
3. Dual-Purpose Utility: The pipeline serves two functions:
   • Automated Tuning: Returns gate voltage targets to set the device to the single-charge regime.
   • Physics-Based Feature Extraction: The segmented line maps allow for the automatic extraction of physical parameters (line slopes, separations, lever arms), providing feedback to fabrication and design teams to improve future device runs.
4. Practical Roadmap: The authors propose a path to real-time integration in cryogenic wafer probers, including pre-filtering defective devices and online confirmation scans.

4. Results

• Overall Success Rate: The model achieved an 80.0% success rate (812/1015) in locating the single-charge regime across the entire heterogeneous dataset.
• Peak Performance: Success rates varied by design, ranging from 61% to 88%, with the best-performing designs (Design D and E) reaching 88%.
• Failure Analysis: The authors identified dominant failure modes:
  • Bad Quality CSDs: Defective devices with low signal-to-noise ratio (SNR) or large blank regions.
  • Faint/Stochastic Lines: Transition lines that are intermittent or low contrast.
  • Spurious Artifacts: Noise-induced false positives.
  • Fragmented Lines: True transitions broken into multiple segments.
• Mitigation Strategies: The paper proposes targeted solutions, such as training a "good vs. bad" CSD classifier to pre-filter data, using online confirmation scans for low-confidence detections, and refining post-processing to merge fragmented segments.

5. Significance

This work represents a practical step toward high-throughput, automated calibration for silicon spin qubits, a critical requirement for scaling quantum processors to thousands of qubits.

• Industrial Relevance: By validating on 300 mm industrial wafers with CMOS-compatible processes, the method bridges the gap between academic lab demonstrations and industrial manufacturing.
• Efficiency: It eliminates the need for expert manual intervention for the vast majority of devices, drastically reducing the time required to characterize and tune quantum arrays.
• Feedback Loop: The ability to extract physical features automatically creates a closed loop between measurement and fabrication, enabling data-driven improvements in device design and process control.
• Future Integration: The lightweight nature of the MobileNetV2-based model makes it feasible for in-situ integration into cryogenic control hardware, paving the way for fully autonomous quantum computer operation.