A Scalable FPGA Architecture for Real-Time Decoding of Quantum LDPC Codes Using GARI

This paper presents a scalable, resource-efficient FPGA architecture for real-time decoding of quantum LDPC codes using the GARI method, which achieves low latency and significantly reduced resource consumption while supporting multiple decoder cores for correlated error correction.

The Gist

Imagine you are trying to solve a massive, incredibly complex jigsaw puzzle. But there's a catch: the pieces are constantly changing shape, and sometimes, when you move one piece, it accidentally knocks over three others nearby. This is what scientists face when trying to fix errors in quantum computers. The "puzzle" is a Quantum LDPC code, and the "pieces" are bits of information that can get corrupted.

This paper introduces a new, super-efficient machine (built on a chip called an FPGA) designed to solve these puzzles in real-time, even when the errors are messy and connected.

Here is the breakdown of their solution using simple analogies:

1. The Problem: The "Messy Room"

In the past, scientists tried to fix quantum errors by looking at them one by one, like a janitor picking up trash in a room. But in quantum computing, errors are often "correlated." This means if one piece of trash falls, it knocks over a whole pile of others.

• The Old Way: Trying to clean up the whole room by looking at every single item individually is slow and requires a huge team of janitors (computers).
• The New Method (GARI): The authors use a clever trick called GARI (Graph Augmentation and Rewiring for Inference). Imagine taking a tangled ball of yarn and carefully untangling it into two separate, neat bundles before trying to clean it up. GARI reorganizes the "mess" so the computer can see the connections between errors clearly, making the cleanup much faster and more accurate.

2. The Solution: A Two-Team Relay Race

The authors built a special hardware decoder (a machine that solves the puzzle) that works like a relay race between two specialized teams. They didn't just build one giant machine; they built a system that shares resources smartly.

• Team A (The Serial Runners): This team handles the "big picture" connections. They work one step at a time, carefully checking the main structure of the puzzle. They are slow but thorough.
• Team B (The Parallel Sprinters): This team handles the smaller, independent pieces. They can work on many pieces at the exact same time because those pieces don't interfere with each other. They are fast and energetic.

The Magic Trick: Instead of building two separate, massive factories for Team A and Team B, the authors built a single factory floor where both teams share the same tools and space.

• When Team A is working, Team B waits.
• When Team A finishes a step, they pass the "baton" (data) to Team B.
• Team B does their sprint, then passes the baton back.
• They use a traffic controller (Crossbar) to make sure the data gets to the right person without crashing into each other.

3. The Result: Fitting More in Less Space

The paper tested this design on a specific, very difficult puzzle (the [[144,12,12]] code).

• The Old Way: To solve this puzzle with the previous best method, you would need a huge warehouse full of computers (48 separate chips) to do it fast enough.
• The New Way: Because this new design is so efficient at sharing space, the authors were able to fit three of these decoding machines onto a single chip.
• The Speed: The machine solves the puzzle in about 596 nanoseconds per round. That is faster than a blink of an eye.

4. Why This Matters

Think of it like upgrading a city's traffic system.

• Before: You needed to build a new highway for every single car (error) to get to its destination. This was expensive and took up too much land (power and space).
• Now: You built a smart roundabout system where cars share the lanes efficiently. You can fit three times as many cars on the same stretch of road, and they get there just as fast.

The Bottom Line:
The authors created a hardware design that is six times more efficient than previous attempts. By using the GARI method to untangle the errors and a smart "relay race" architecture to share resources, they proved that you can fix complex, messy quantum errors quickly and cheaply. This is a crucial step toward making large-scale quantum computers a reality, as it means we won't need a massive, power-hungry supercomputer just to keep the quantum computer running.

Technical Summary

1. Problem Statement

The realization of large-scale fault-tolerant quantum computing requires real-time decoders for Quantum Error Correction (QEC). Current challenges include:

• Correlated Errors: Standard decoders often treat X and Z errors independently, leading to suboptimal performance when Y errors (which create correlations between X and Z) are present.
• Scalability Bottlenecks: Existing hardware implementations for Quantum Low-Density Parity-Check (QLDPC) codes, such as bivariate bicycle codes, struggle to scale. Fully parallel approaches on FPGAs exhaust resources (Block RAMs, routing) at relatively low code distances (e.g., $d=12$), preventing the deployment of multiple decoder cores on a single device.
• Power and Latency: Multi-FPGA solutions to overcome resource limits introduce high power consumption and communication complexity, which is unsustainable for the classical control infrastructure of large quantum processors.
• Precision Uncertainty: There is a lack of systematic analysis regarding the impact of reduced numerical precision on detector error models with correlated errors.

2. Methodology

The authors propose a novel hardware architecture based on the Graph Augmentation and Rewiring for Inference (GARI) method. The methodology involves three key components:

A. The GARI Transformation

The decoder utilizes the GARI technique to modify the correlated detector error model. By eliminating 4-cycles involving Y-type errors and restructuring the decoding graph via matrices $U$ and $V$, the method separates correlated components while enabling joint decoding through the exchange of reliability information. This transforms the problem into a structure where:

• $D_X$ and $D_Z$ matrices represent the primary error domains.
• $U$ and $V$ matrices handle the correlations.

B. Hybrid Architecture Design

Instead of a fully parallel approach, the architecture employs controlled parallelism and resource reuse by splitting the decoding process into two specialized units:

1. $D_X, D_Z$ Unit (Serial Scheduler):
   • Processes the main error matrices ($D_X$ and $D_Z$) using a serial Belief Propagation (BP) schedule.
   • Uses a "ping-pong" buffer strategy to alternate between processing $D_X$ and $D_Z$ on the same hardware, minimizing resource usage.
   • Employs memory-based storage for variable nodes to avoid the massive interconnect overhead of register-based designs.
2. $U, V$ Unit (Parallel Scheduler):
   • Exploits the fact that checks within $U$ and $V$ are independent.
   • Uses a fully parallel architecture to process these matrices simultaneously.
   • Includes a specialized Crossbar Interconnect to route messages between $U$ and $V$ tiles. This crossbar uses a tag-based, controller-less routing mechanism (similar to radix sorting) to distribute messages efficiently without complex control logic.

C. Data Flow and Synchronization

• The system alternates between the serial and parallel units. Data flows from $D_X \to U$, then $V \to U, D_Z$, and so on.
• A Convergence Checking Unit aggregates parity results in parallel to determine if decoding has terminated.
• The architecture is designed to balance the processing time of the serial and parallel units to avoid idle cycles.

3. Key Contributions

• First Multi-Core Implementation for Correlated Errors: The paper reports the first implementation of multiple decoder cores targeting correlated errors on a single FPGA device.
• Resource Efficiency: By combining serial and parallel scheduling and reusing resources, the architecture achieves a 6x reduction in hardware resources compared to previous GARI-based proposals.
• Scalable Ensemble Decoding: The design allows for the implementation of an ensemble of three decoder cores on a single VCU19P FPGA, whereas previous approaches could only fit one uncorrelated decoder.
• Energy-Conscious Scaling: The architecture reduces the number of required FPGA devices for a full ensemble (reducing 48 devices to 8 for a specific target), significantly lowering power consumption and inter-board communication overhead.

4. Results

The architecture was implemented on an AMD VCU19P FPGA targeting the [[144, 12, 12]] bivariate bicycle code.

• Resource Utilization (Single Core):
  • Occupies ~7.5% of LUTs, 3.5% of Registers, and 26% of BRAMs.
  • Allows for three instances (an ensemble) on a single chip, utilizing ~90% of available BRAMs.
• Latency Performance:
  • Clock Frequency: ~274 MHz (3.647 ns period).
  • Single Decoder Latency: Average of 14.4 µs per decoding round (assuming 2.28 iterations).
  • Ensemble Latency: With an ensemble of 24 decoders distributed across 8 FPGAs, the average latency per round is 7.16 µs.
  • Per-Round Latency: The system achieves 596 ns per decoding round, meeting strict real-time constraints.
• Quantization: The design uses 6-bit LLR inputs, 8-bit check-node messages, and 10-bit variable-node messages, achieving accuracy close to floating-point implementations.
• Comparison: The proposed solution fits three correlated-error decoders on one FPGA, whereas prior work ([11]) could only fit one uncorrelated decoder.

5. Significance

This work addresses a critical bottleneck in the path to fault-tolerant quantum computing: the classical decoding infrastructure.

• Feasibility of QLDPC: It demonstrates that complex QLDPC codes with correlated errors can be decoded in real-time on classical hardware without prohibitive resource costs.
• Power Efficiency: By enabling multiple cores per chip, the approach drastically reduces the power budget required for the classical control layer, a major concern for scaling quantum systems.
• Future Pathway: The architecture provides a scalable blueprint for integrating ensemble-based decoding, which is essential for improving logical error rates in future quantum processors. The authors plan to extend this to full ensemble integration on a single chip and explore ASIC implementations.