Impact of Surface Treatment on Noise in PL-Measurements of Silicon Vacancies in 4H-SiC Lateral pin-Diodes

This study demonstrates that integrating thermally grown oxides with nitrogen monoxide annealing and atomic layer etching into lateral pin-diodes effectively eliminates surface-induced noise and damage, significantly enhancing the signal-to-noise ratio and electrical performance of silicon vacancies in 4H-SiC for quantum applications.

The Gist

The Big Picture: Finding a Needle in a Haystack

Imagine you are trying to find a single, tiny, glowing firefly (a Silicon Vacancy) inside a massive, dark warehouse. This firefly is special because it can be used for future quantum computers and ultra-sensitive sensors.

The problem? The warehouse is filled with other, much brighter, fake lights (called background noise) created by the construction workers who built the warehouse. These fake lights are so bright that they completely drown out the tiny firefly, making it impossible to see or study.

This paper is about cleaning up the warehouse so the firefly can finally shine.

The Problem: Construction Damage

To build the devices needed to control these fireflies, scientists have to use heavy industrial tools like lasers, plasma, and chemical baths. Think of these tools as construction crews.

• The Issue: When these crews work, they often leave behind "construction dust" and "scratches" on the walls of the warehouse. In scientific terms, this is surface damage.
• The Result: This damage creates its own bright, messy glow (noise). In the paper's experiments, a standard construction method (using plasma) made the warehouse so bright that the firefly was invisible. It was like trying to watch a candle in a stadium lit by a thousand floodlights.

The Solution: Gentle Cleaning and Better Coatings

The researchers tested different ways to clean the walls and coat them to stop the noise. They found two main strategies:

1. The "Thermal Oven" vs. The "Plasma Blaster"

• The Bad Way (Plasma): Imagine using a high-pressure firehose (plasma) to clean the walls. It gets the job done fast, but it blasts the surface, creating deep scratches and new glowing defects. This made the noise worse.
• The Good Way (Thermal Oxidation): Instead of blasting, they used a gentle oven process. They heated the silicon to grow a thin, perfect layer of glass (oxide) on the surface. This is like laying down a pristine, smooth carpet over the rough floor. This method produced almost zero noise.
• The Secret Ingredient: They found that baking this new glass layer with a specific gas (Nitrogen Monoxide) made it even smoother and quieter, like polishing the glass until it was invisible.

2. The "Sandpaper" vs. The "Micro-Scalpel"

• The Bad Way (Reactive Ion Etching - RIE): To make the devices, they sometimes have to carve shapes into the silicon. The standard method (RIE) is like using coarse sandpaper. It shapes the silicon but leaves it rough and noisy.
• The Good Way (Atomic Layer Etching - ALE): They tried a new technique called ALE. Imagine using a micro-scalpel that removes the surface one single atom at a time. It is incredibly slow, but it leaves the surface perfectly smooth.
• The Magic Combo: Even if they used the rough sandpaper first, following it up with the micro-scalpel completely erased the damage. The surface ended up just as quiet as if they had never used the sandpaper at all.

The Final Device: The "Optical Window"

The researchers built a special device called a lateral pin-diode. Think of this as a high-tech control panel for the firefly.

• They realized that the layers of insulation and metal covering the device were the source of the noise.
• They created an "Optical Window." This is a small, carefully carved-out area where they stripped away all the noisy, rough layers, leaving only the perfect, smooth glass coating (the thermally grown oxide) right next to the firefly.

The Results: A Crystal Clear View

When they looked at the fireflies through this new "Optical Window":

• Near the surface: The signal became 15 times clearer than before.
• Deeper down: The signal became 50 times clearer.
• Electrical Performance: Crucially, cleaning up the surface didn't break the device's electronics. The diode still worked perfectly, blocking high voltage and leaking almost no current.

Summary

The paper proves that if you want to use silicon vacancies for quantum technology, you cannot just use standard, rough industrial processes. You must treat the surface with extreme gentleness. By swapping "plasma blasting" for "gentle baking" and "coarse sanding" for "atomic-level shaving," they created a silent, clean environment where these tiny quantum fireflies can finally be seen and controlled.

Technical Summary

Technical Summary: Impact of Surface Treatment on Noise in PL-Measurements of Silicon Vacancies in 4H-SiC Lateral pin-Diodes

Problem Statement
Silicon vacancies (VSi) in 4H-SiC are promising candidates for quantum technologies due to their long spin coherence times and compatibility with mature semiconductor processing. However, integrating these color centers into complex lateral device structures, such as pin-diodes or nanophotonic waveguides, requires extensive fabrication flows involving hundreds of processing steps. Conventional CMOS-compatible processing, particularly dry etching and plasma-based deposition, introduces significant photoluminescence (PL) noise. This noise originates from optically active defects generated in the surface-near crystal or at layer interfaces. This background luminescence often outshines the intrinsic emission of VSi, especially for near-surface emitters, and degrades spectral resolution by broadening resonant photoluminescent excitation (PLE) linewidths. Consequently, this reduces coherence times, relaxation times, and overall measurement sensitivity, posing a severe hurdle for high-precision quantum sensing and computing applications relying on off-resonant excitation.

Methodology
The study employs a systematic approach to quantify the impact of individual processing steps on PL noise and to optimize surface passivation strategies.

• Sample Preparation: Experiments utilized 5 mm × 5 mm chips from a single 4H-SiC wafer with a 10 µm thick n-type epitaxial layer to ensure material uniformity. Samples underwent various surface modifications, including different passivation deposition techniques (plasma-enhanced vs. thermal), surface treatments (HF dip, Caro's acid), and etching processes.
• Characterization:
  • Confocal PL: A commercial SQUTEC setup with a 730 nm laser (0.25 mW) and a 100x objective (NA=0.9) was used for off-resonant excitation at room temperature. Depth-resolved PL profiles were recorded to distinguish surface/interface noise from bulk emission.
  • Statistical Analysis: PL intensity distributions within ±100 nm of the surface were extracted and visualized using violin plots to compare background levels across different processing conditions.
  • In-line Inspection: A custom-built automated surface inspection tool (Intego) performed full-wafer PL mapping before and after critical steps (e.g., ion implantation, annealing) to monitor process-induced changes non-destructively.
  • Device Fabrication: Lateral pin-diodes were fabricated on both c-plane and a-plane wafers using a CMOS-compatible process. Three designs were tested: a reference with full passivation stacks, one with dry-etched SiC surfaces, and one with an "optical window" where layers were selectively etched down to a thermally grown oxide.
• Defect Generation: Color centers were generated via electron irradiation (10 MeV, effective 4.5 MeV) followed by vacuum annealing at 600 °C.

Key Contributions and Results

1. Identification of Noise Sources: The study demonstrates that plasma-based processes (CCP PECVD, RIE) significantly degrade surface quality, increasing background PL by factors of 4 to 8 compared to bare surfaces due to ion-induced damage. In contrast, thermally grown oxides and low-pressure chemical vapor deposition (LPCVD) layers exhibit minimal background noise.
2. Optimization of Passivation:
   • Thermal Oxidation: Thermally grown SiO2, particularly when followed by nitrogen monoxide (NO) annealing, provides the lowest background PL (<0.5 kcounts/s) and remains stable during subsequent 600 °C annealing required for color center activation.
   • Etching Strategy: While Reactive Ion Etching (RIE) causes severe surface damage, the combination of RIE followed by Atomic Layer Etching (ALE) completely removes the induced damage, restoring surface quality to levels comparable to ALE-only processes.
   • Annealing Stability: Plasma-deposited films (PEALD Al/Hf oxides) and unpassivated surfaces degrade significantly under 600 °C annealing, whereas thermally grown oxides maintain low noise levels.
3. Device Integration and Performance:
   • Optical Window Design: Lateral pin-diodes featuring an optical window etched down to the thermally grown oxide layer successfully eliminated the parasitic PL from the passivation stack.
   • Signal-to-Noise Ratio (SNR): These optimized devices achieved an SNR of 15 for near-surface emitters and up to 50 for deeper emitters on both c-plane and a-plane wafers.
   • Single Emitter Verification: Second-order intensity autocorrelation ($g^{(2)}$) measurements confirmed single-emitter behavior with a dip below 0.5. The noise floor inside the optical window was sufficiently low to resolve the dip clearly, whereas measurements outside the window showed degraded dips due to background noise.
   • Electrical Properties: The devices maintained ideal electrical characteristics, blocking up to 150 V with leakage currents below 10 pA/µm. Electron irradiation and subsequent annealing had negligible impact on the I-V characteristics, ensuring that the optical improvements did not compromise electrical performance.

Significance
The paper establishes that minimizing background PL noise is critical for the practical application of VSi in 4H-SiC for quantum technologies. By identifying specific processing steps that generate optically active defects and demonstrating effective mitigation strategies—specifically the use of thermally grown oxides with NO annealing and ALE finishing—the work enables the integration of high-quality color centers into complex lateral semiconductor devices. The successful fabrication of lateral pin-diodes with high SNR and excellent electrical blocking capabilities provides a viable pathway for scalable quantum sensing and computing platforms that require Stark shift tuning and resonant excitation. The study further validates in-line PL mapping as a rapid, non-destructive tool for process optimization and defect monitoring in quantum device manufacturing.