Hardware-aware Low-latency Quantum Compilation with Data-driven Lightweight Error Detection for Early Fault-Tolerant Systems

This paper presents a hardware-aware, data-driven framework that jointly optimizes quantum compilation and lightweight error detection to significantly improve algorithmic success rates for early fault-tolerant systems under latency constraints.

The Gist

Imagine you are trying to send a delicate message across a noisy, crowded room using a walkie-talkie. The signal is weak, the static is loud, and if you try to talk too fast, the message gets garbled. This is the current state of quantum computers: they are powerful but incredibly fragile, prone to "noise" that ruins calculations.

This paper presents a new "smart system" designed to help these computers get their messages through clearly, even before we have perfect, error-proof machines. Here is how it works, broken down into simple concepts:

1. The Problem: Two Separate Teams Not Talking

Currently, building a quantum program involves two separate steps that don't really talk to each other:

• The Traffic Controller (Compiler): This team decides which "worker" (qubit) does which job and how they pass notes to each other. They try to find the shortest path to avoid traffic jams.
• The Safety Inspector (Error Detection): This team adds a "spot check" system. If a worker makes a mistake, the inspector catches it and says, "Throw this result away and try again."

The problem is that the Traffic Controller doesn't know about the Safety Inspector's rules, and the Inspector doesn't know where the Traffic Controller is sending the workers. They work in isolation, often wasting time or missing opportunities to fix errors.

2. The Solution: A "Smart Co-Pilot"

The authors built a unified system that acts like a smart co-pilot, handling both traffic and safety at the same time. It uses two main tools:

• The Traffic Optimizer (Hardware-Aware Compilation):
  Instead of just finding the shortest path, this optimizer looks at the "health" of every worker. Some workers are tired (noisy) or slow. The system rearranges the workers so the most important tasks are done by the healthiest, most reliable workers. It uses a mathematical "score" that penalizes paths that are likely to fail, ensuring the message stays clear.

• The Data-Driven Safety Scheduler (QED Scheduler):
  This is the "brain" of the operation. It uses a machine learning model (a type of AI called XGBoost) that has been trained on millions of simulated scenarios.

  • How it learns: Imagine teaching a student by showing them 50,000 different practice tests with different types of noise. The student learns to predict: "If we check for errors here, we save the day. If we check there, we waste time."
  • How it works: When a new program arrives, this AI instantly (in less than a blink of an eye) decides exactly when and where to place the safety checks. It balances the need for safety against the risk of throwing away too many results.

3. The "Super-Additive" Magic

The most exciting finding is what happens when you combine these two tools.

• If you just fix the traffic, you get a small improvement.
• If you just add safety checks, you get a small improvement.
• But when you do both together? The improvement is greater than the sum of the parts.

The Analogy: Think of it like a relay race.

• Fixing traffic is like making sure the runners are in the right lanes so they don't trip.
• Safety checks are like having a coach yell "Watch out!" if someone stumbles.
• Doing both: Because the runners are in the right lanes (good traffic), they are less likely to stumble. This means the coach's "Watch out!" calls are more reliable and less distracting. The team runs faster and more accurately than if you just had good lanes or just a coach alone.

4. The Results: Faster and More Reliable

The team tested this system on a supercomputer using powerful graphics cards (GPUs) to simulate quantum computers with up to 20 qubits. They ran famous quantum algorithms (like VQE and Grover's algorithm) under three different "noise" conditions (simulating different types of hardware).

• Success Rate: On an 8-qubit test, their system increased the chance of getting a correct answer by 68% compared to the standard method (SABRE).
• Speed: Even though they added extra safety checks, the total time to run the program stayed under one second, which is fast enough for current cloud quantum computers.
• Real-World Check: They also ran a small test on a real IBM quantum computer. The real results were slightly lower than the simulation (due to unpredictable real-world "drift" and interference), but the ranking remained the same: their smart system still beat the standard method.

5. The Bottom Line

This paper doesn't claim to have solved all quantum errors. Instead, it offers a practical "bridge" for the current era of noisy computers. By using a smart, data-driven approach to coordinate where the work happens and when to check for mistakes, they can significantly boost the success rate of quantum calculations today, without needing thousands of extra "perfect" qubits.

In short: They taught the quantum computer's traffic controller and safety inspector to work as a single, highly efficient team, resulting in much clearer messages in a very noisy room.

Technical Summary

Technical Summary: Hardware-aware Low-latency Quantum Compilation with Data-driven Lightweight Error Detection

1. Problem Statement

Noisy Intermediate-Scale Quantum (NISQ) processors face fundamental limits imposed by gate infidelities, limited connectivity, and finite coherence times. While full Quantum Error Correction (QEC) could theoretically overcome these limits, it requires prohibitive qubit overheads (hundreds to thousands of physical qubits per logical qubit). Consequently, the field is entering an "early fault-tolerance" regime where lightweight error detection (QED) using distance-two stabilizer codes offers constant-overhead noise suppression via post-selection.

However, a critical gap exists in current toolchains: qubit mapping/routing and QED syndrome scheduling are treated as isolated problems.

• Existing compilers (e.g., SABRE) optimize for connectivity and latency but ignore the ancilla overhead and post-selection penalties associated with QED.
• Existing QED studies assume a fixed, pre-compiled circuit, failing to account for how routing choices affect the residual error presented to the detection layer.

This decoupling prevents the realization of available fidelity gains. Furthermore, there is no principled framework to balance detection overhead against success probability under strict latency constraints.

2. Methodology

The paper proposes an integrated, hardware-aware co-design framework that jointly optimizes qubit mapping, SWAP insertion, and syndrome-schedule placement. The system consists of three primary components:

A. Hardware-Aware Compilation Pass
The compiler extends the Qiskit transpiler with a four-stage pipeline:

1. Front-end Ingestion: Parses logical circuits into a Directed Acyclic Graph (DAG) and constructs a weighted interaction graph.
2. Heuristic Initial Allocation: Uses subgraph isomorphism to map high-frequency qubit pairs to high-fidelity device edges.
3. Simulated Annealing (SA) with ILP Kernel: The core optimization loop. It iteratively proposes mapping changes (swapping logical qubits). For sub-circuits within a window size $w$ (typically 10 qubits), an embedded Integer Linear Programming (ILP) solver finds the locally optimal assignment.
   • Cost Function: The optimization is guided by a noise-weighted cost function (Eq. 2) that penalizes expected gate infidelity and latency budget violations. This cost function is formally connected to first-order Depolarising infidelity bounds (Proposition 1).
4. SWAP Insertion & Reduction: Inserts SWAP gates using A*/SABRE heuristics and applies KAK decomposition to cancel redundant rotations.

B. Data-driven QED Scheduler
A machine learning module operates alongside the compiler to determine the optimal placement and frequency of QED blocks:

• Primitives: Uses $[[n, n-2, 2]]$ detection codes with one ancilla per block.
• Feature Extraction: Computes six scalar features per circuit, including two-qubit gate count, critical-path depth, connectivity entropy, and mean local gate fidelity.
• Model: Two XGBoost regressors predict the marginal success gain ($\Delta S$) and post-selection retention ($R$).
• Inference: The scheduler evaluates a utility function (Eq. 3) across a discrete set of syndrome frequencies and block positions, selecting the Pareto-optimal configuration in under 6 ms.

C. HPC-Accelerated Evaluation Framework
The framework utilizes the NVIDIA cuQuantum SDK for GPU-accelerated density-matrix simulation (up to 20 qubits) to generate training data and validate results. It employs SLURM for job scheduling and Docker for reproducibility.

3. Key Contributions

1. Joint Co-Design Formulation: A unified optimization objective that couples qubit mapping and QED scheduling, penalizing both expected infidelity and latency/retention constraints.
2. Noise-Weighted Cost Function: A formal cost function (Eq. 2) that generalizes previous noise-adaptive mapping approaches (e.g., Murali et al.) by incorporating circuit-path importance weights and is proven to minimize a first-order upper bound on circuit infidelity.
3. Data-Driven Scheduler: An XGBoost-based scheduler trained on 50,000 circuit-noise pairs that predicts success uplift and retention, enabling rapid selection of optimal syndrome schedules.
4. Comprehensive Evaluation: An HPC-based evaluation harness using cuQuantum to benchmark the framework across VQE, Phase Estimation, and Grover algorithms on three distinct noise profiles (Superconducting, Trapped-ion, and Adversarial).

4. Experimental Results

Experiments were conducted on circuits ranging from 6 to 20 qubits with depths of 10–160.

• Success Probability Gains: The joint co-design approach significantly outperforms the standard SABRE baseline.
  • On an 8-qubit VQE instance (Superconducting profile), success probability increased by 68% (95% CI: 60%–76%).
  • On a 12-qubit QPE instance, the improvement reached 118%.
  • Gains were consistent across Trapped-ion (15–28%) and Adversarial (31–45%) noise profiles.
• Super-Additive Interaction: Ablation studies revealed that the combined effect of the mapping pass and QED scheduler is greater than the sum of their individual parts. For VQE-H2, the joint gain ($\Delta S = +0.26$) exceeded the sum of individual gains ($\Delta S_{mapper} + \Delta S_{QED} = 0.17$). This is attributed to noise-aware routing reducing residual errors, thereby improving syndrome reliability.
• Latency and Retention:
  • End-to-end latency increased by a factor of 1.7–2.1 but remained under 1 second, compatible with cloud pre-processing pipelines.
  • Post-selection retention remained above 32% for the 8-qubit VQE instance, demonstrating that the overhead is manageable.
• Hardware Validation: Small-scale validation on an IBM Eagle-family processor confirmed directional consistency with simulations. However, hardware results were 4–8 percentage points lower than simulations, attributed to unmodelled drift, spectator cross-talk, and calibration staleness.

5. Significance and Claims

The paper claims that its integrated framework addresses a fundamental tension in early fault-tolerance: the trade-off between detection overhead and algorithmic success. By treating compilation and error detection as a coupled problem rather than isolated steps, the system unlocks fidelity gains that are inaccessible to either component alone.

The authors emphasize that:

• The approach is hardware-aware, leveraging specific device calibration data (fidelities, coherence times) to guide compilation.
• The data-driven scheduler provides a practical, low-latency method to navigate the complex trade-off space between success probability and shot retention.
• The super-additive interaction between mapping and detection proves that optimizing the "noise environment" presented to the error detection layer is critical for maximizing its utility.

The work is presented as a step toward practical early fault-tolerance, offering a reproducible pipeline (via Docker/SLURM) that bridges the gap between theoretical error detection codes and the realities of noisy, constrained quantum hardware. The authors note limitations, including the reliance on simulation for absolute values, the need for scheduler retraining during device drift, and the current restriction of exact simulation to ~20 qubits.