Lattice surgery for near-term experimental logical qubit entanglement creation in planar architectures

This paper details a lattice surgery-based logical teleportation protocol for superconducting qubit architectures, analyzing modularity constraints and optimizing interface sizes and decision logic to demonstrate near-term improvements for entangling logical qubits in early fault-tolerant quantum computing.

The Gist

Imagine you are trying to send a fragile, secret message from one room to another in a noisy, chaotic building. In the world of quantum computing, these "rooms" are logical qubits (groups of physical qubits working together to protect information), and the "noise" is the constant interference that causes errors.

This paper is like a detailed blueprint for a specific method called Lattice Surgery. It explains how to move a quantum state from one logical qubit to another (a process called teleportation) using a superconducting chip, while keeping the message safe from errors.

Here is the breakdown of their work using simple analogies:

1. The Setup: Two Islands and a Bridge

Think of your quantum computer as a grid of tiny islands (physical qubits). To do useful work, you group these islands into two larger "super-islands" (logical qubits).

• The Problem: You want to move a secret state from Super-Island A to Super-Island B. But you can't just fly the state over; the islands are separated by a gap.
• The Solution (Lattice Surgery): Instead of building a long bridge, you temporarily merge the two islands by placing a small row of "helper" qubits between them. You measure these helpers to create a connection, move the information, and then cut the connection back apart. This is the "surgery."

2. The Experiment: The "Surface-41" Chip

The authors tested this idea on a specific, small-scale design they call the Surface-41 chip.

• Imagine two small squares (each made of 17 qubits, called "Surface-17") sitting side-by-side.
• Between them, they place a narrow strip of 3 extra qubits.
• This entire setup (17 + 3 + 17 = 37, plus a few more for measurement) is their testbed. They simulated how well this setup works using error rates taken from real experiments at ETH Zurich.

3. The Big Question: How Much "Surgery" Do We Need?

The paper explores two main ways to make this process more efficient:

A. The "Lazy" vs. "Strict" Approach (Modularity)

Usually, to ensure the message isn't corrupted, you check the work constantly.

• The Strict Way (Fully Modular): You check the work completely after every single step (initializing, merging, splitting). It's like a teacher checking a student's homework after every single sentence they write. It's very safe, but it takes a long time.
• The "Lazy" Way (Depleted): You only check the work when absolutely necessary to ensure the final result is correct. You skip some intermediate checks if the previous ones looked good.
• The Result: The authors found that the "Lazy" way is actually twice as good at preserving the message. By skipping unnecessary checks, the qubits spend less time "sitting around" (idling), which is when they are most likely to get corrupted by noise.

B. The "Smart" Approach (Adaptive Logic)

This is like having a traffic light that changes based on real-time traffic.

• Standard Way: You always run a full set of checks, even if the first one told you everything is fine.
• Adaptive Way: You run the first check. If it says "All Clear," you skip the second check. If it says "Problem," you run the second check.
• The Catch: To do this, the computer needs to think fast. It has to process the result of the first check and decide what to do next. This takes time (called latency).
• The Result: This "Smart" approach works great only if the computer is fast enough. If the decision-making takes too long (more than about 200 nanoseconds for current hardware), the qubits sit idle too long, and the noise ruins the message. However, if the hardware is fast, this method can improve success rates by about 10%.

4. The "Bridge Width" Discovery

The authors also asked: "What if we make the bridge between the islands wider? Maybe more qubits in the middle will make the connection stronger?"

• The Analogy: Imagine building a bridge between two cliffs. You might think a wider bridge with more planks is safer.
• The Finding: In quantum computing, wider is worse. Every extra qubit in the middle is another place where an error can happen. The simulation showed that adding more qubits to the gap always increased the chance of failure.
• Conclusion: The best strategy is to keep the gap as narrow as possible (just one column of qubits).

5. The Future Outlook

The paper concludes that for these quantum computers to work reliably in the near future:

1. We need to reduce the physical error rates of the hardware by about 45% (a factor of 0.55) to see the benefits of scaling up to larger, more complex chips.
2. We should stick to the narrowest possible connections between logical qubits.
3. We should use "depleted" (less frequent) checking and "adaptive" (smart) logic, provided our control electronics are fast enough to keep up.

In summary: The paper provides a recipe for moving quantum information between two groups of qubits. It argues that the most efficient way to do this is to keep the connection narrow, skip unnecessary safety checks, and use smart, real-time decision-making—but only if the computer can make those decisions quickly enough to avoid the noise.

Technical Summary

Technical Summary: Lattice Surgery for Near-Term Experimental Logical Qubit Entanglement Creation in Planar Architectures

Problem Statement
In the era of early fault-tolerant (FT) quantum computing, a critical milestone is the demonstration of entanglement operations between logical qubits. While superconducting qubit platforms have successfully demonstrated logical qubit initialization and error correction (extending coherence times), performing logical entangling operations on planar architectures remains challenging. This difficulty arises because transversal entangling gates are prohibited by the inherent nearest-neighbor connectivity constraints of 2D superconducting chips. Consequently, alternative schemes are required to create entanglement between logical qubits without incurring prohibitive overheads in physical qubits and gate counts. The specific challenge addressed is the implementation of a logical teleportation protocol between two surface code logical qubits using lattice surgery, optimized for the constraints and noise characteristics of superconducting transmon architectures.

Methodology
The authors propose and simulate a logical teleportation protocol based on lattice surgery, specifically designed for a "surface-41" chip architecture. This layout consists of two distance-$d=3$ rotated surface code patches (Surface-17) separated by a column of three physical data qubits, effectively forming a $3 \times 7$ rotated surface code.

The study employs a multi-faceted approach:

1. Protocol Definition: The authors detail the four-step lattice surgery process: initialization, merging (joint parity measurement), splitting, and measurement. This involves measuring joint stabilizers at the interface of the two code patches to reconstruct logical parity.
2. Noise Modeling: Simulations utilize an incoherent circuit-level Pauli noise model parameterized by experimental data from a superconducting surface-code device (ETH Zurich/QuDev). The model includes stochastic errors in state preparation and measurement, depolarizing noise following gates, and decoherence ($T_1, T_2$) during idle times. Gate durations are set to realistic values (40 ns for single-qubit, ~100 ns for two-qubit, 400 ns for measurement).
3. Protocol Variants: The study compares different scheduling strategies for stabilizer measurements:
   • Fully Modular: Each stage (initialization, merging, splitting) undergoes a full Quantum Error Correction (QEC) round independently.
   • Depleted: Stabilizer readouts are reduced to the minimum necessary to guarantee fault tolerance for the entire teleportation protocol, removing redundant rounds in intermediate stages.
   • Adaptive (In-Sequence): A decision logic is introduced where subsequent stabilizer measurements are conditioned on previous outcomes. If the first measurement agrees with the expected value, the second round is omitted, reducing average circuit depth at the cost of decision latency.
4. Scalability Analysis: The authors investigate the impact of increasing the code distance ($d$) and the width ($w$) of the interface region (the number of data qubits between patches) on logical error rates.

Key Contributions

• Detailed Protocol Specification: The paper provides a comprehensive description of logical teleportation via lattice surgery at both logical and physical qubit levels, tailored for superconducting architectures.
• Overhead Reduction Analysis: It demonstrates that a "depleted" scheduling scheme, which minimizes stabilizer readouts while maintaining global fault tolerance, significantly outperforms the fully modular approach.
• Adaptive Logic Evaluation: The work quantifies the trade-off between the benefits of adaptive syndrome extraction (reduced gate count) and the penalties of decision latency. It identifies specific parameter regimes where adaptive logic yields a net performance gain.
• Interface Optimization: The study rigorously tests the hypothesis that increasing the physical separation (width $w$) between code patches might improve protection. It concludes that minimizing the interface width is optimal.

Results

• Depleted vs. Modular: For the Surface-17 code ($d=3$), the depleted scheme improves logical teleportation fidelity by a factor of approximately 2 compared to the fully modular scheme across a range of physical error rates. This improvement is attributed to the reduction in circuit depth and idle time.
• Adaptive Logic: The adaptive depleted scheme offers a performance advantage over the standard depleted scheme only if the decision latency is sufficiently low. For near-term realistic improvements ($\lambda \in [0.1, 1]$), latency must be $\lesssim 200$ ns. In the limit of vanishing error rates and zero latency, the adaptive scheme offers a maximal improvement of $\sim 10\%$. However, for high error rates or large latencies, the adaptive scheme becomes disadvantageous due to accumulated idle errors.
• Interface Width: Simulations for code distances $d=3, 7, 11$ and interface widths $w=1, 3, \dots, 15$ show a clear linear increase in logical error probability as the width $w$ increases. There is no scenario where adding extra qubits in the interface region improves fidelity; thus, a single column of data qubits ($w=1$) is optimal.
• Threshold Estimation: To achieve exponential suppression of logical errors for larger distances ($d$ up to 19), the physical error rates must be reduced by a factor of $\lambda_{th} \approx 0.55$ relative to current experimental benchmarks. Below this threshold, increasing the distance effectively suppresses logical errors.

Significance and Claims
The paper claims to provide design guidelines for near- and mid-term experimental devices aiming to perform fault-tolerant logical operations. Its primary significance lies in demonstrating that:

1. Logical entanglement via lattice surgery is feasible on planar superconducting architectures with modest overhead.
2. Optimizing the schedule of measurements (depleted and adaptive schemes) is as critical as the physical hardware parameters for achieving high-fidelity logical operations.
3. The "optimal" design for the interface between logical patches is the minimal possible size, countering potential intuitions that larger interfaces might offer better protection.

The authors position this work as a projection for near-term experiments, focusing on the comparative analysis of protocol variants and their fault-tolerance aspects rather than proposing a specific microscopic hardware implementation. They note that while leakage and crosstalk are not explicitly modeled, the simplifications are justified by the ability to reproduce experimental outcomes under these assumptions.