A Native RTL Quantum Statevector Simulator in FP64 on an HBM-Equipped FPGA
This paper presents a native Verilog RTL implementation of a high-performance FP64 quantum statevector simulator on an HBM-equipped FPGA that achieves perfect fidelity for up to 15 qubits by translating a validated HLS kernel into hand-written logic with specialized gate engines and an optimized HBM memory architecture, while also documenting a specific verification failure for 16 or more qubits.