Designing Short-Stage CDC-XPUFs: Balancing Reliability, Cost, and Security in IoT Devices

1. Problem Statement

The rapid expansion of the Internet of Things (IoT) requires security mechanisms that are both robust and resource-efficient. While Physically Unclonable Functions (PUFs) offer a lightweight alternative to traditional cryptography, existing designs face two critical vulnerabilities:

• Machine Learning (ML) Attacks: Traditional Arbiter PUFs (APUFs) are linear and easily modeled by ML algorithms. XOR-PUFs (combining multiple APUFs via XOR gates) improve ML resistance but require increasing the number of XOR components (streams) to maintain security, which drastically increases hardware complexity, power consumption, and challenge transmission overhead.
• Reliability-Based Attacks: PUFs are sensitive to environmental noise (temperature, voltage), leading to inconsistent responses for the same challenge. Adversaries exploit this variability (reliability-based attacks) to model PUF behavior. While protocols exist to limit repeated queries, they are costly. Furthermore, standard reliability enhancement techniques (like majority voting) often fail to provide fundamental security against these attacks.

There is a gap in current designs: architectures that simultaneously resist ML attacks, ensure high reliability against noise, and remain lightweight enough for constrained IoT devices.

2. Methodology

The authors propose a unified framework integrating two key innovations into a Component-Differentially Challenged XOR-PUF (CDC-XPUF) architecture:

A. Pre-Selection Strategy for Reliability

Instead of relying on post-processing or majority voting, the authors introduce a hardware-level pre-selection strategy to filter out unstable Challenge-Response Pairs (CRPs) before they are used.

• Mechanism: For every challenge, the system evaluates three potential responses by manipulating delay paths (using additional delay modules like NOT or AND gates).
  • Response 1: Standard path ($d_{upper} - d_{lower}$).
  • Response 2: Upper path delayed ($d_{upper} + \Delta D - d_{lower}$).
  • Response 3: Lower path delayed ($d_{upper} - (d_{lower} + \Delta D)$).
• Selection Criteria: A CRP is only accepted if all three responses are consistent (e.g., "000" or "111"). This ensures the absolute delay difference $|\Delta D|$ is significantly larger than the noise margin, guaranteeing near-perfect reliability and eliminating the variability required for reliability-based attacks.

B. Lightweight Short-Stage CDC-XPUF Design

To address the high hardware cost and challenge transmission overhead of traditional CDC-XPUFs, the authors propose an optimized architecture:

• Shorter Stages: They reduce the number of delay stages within each individual APUF component. This reduces the hardware footprint (multiplexers and arbiters) and power consumption per component.
• More Components: To compensate for the reduced linearity caused by fewer stages, they increase the number of APUF components (streams) in the XOR structure.
• Differential Challenges: Unlike standard XOR-PUFs where all components receive the same challenge, CDC-XPUFs assign unique challenge bits to each component. This expands the CRP space exponentially without requiring longer challenge bits per component, maintaining high non-linearity against ML attacks.

3. Key Contributions

1. Hardware-Level Reliability Enhancement: The introduction of a pre-selection strategy that filters CRPs based on delay difference magnitude, effectively neutralizing reliability-based attacks without significant hardware overhead.
2. Optimized CDC-XPUF Architecture: A novel design that balances security and efficiency by trading stage depth for component width (more components, fewer stages), specifically tailored for IoT constraints.
3. Comprehensive Validation: Extensive experimental validation on FPGA platforms (Artix-7) demonstrating that the proposed design achieves a balance of high reliability, strong ML resistance, and low hardware cost.

4. Experimental Results

The authors tested their designs on Xilinx Artix-7 FPGAs using 100 million generated CRPs.

• Reliability (Bit Error Rate - BER):

  • Standard APUFs and XOR-PUFs showed high BER (e.g., 0.67% to 7.6%).
  • Applying the pre-selection strategy with 2 NOT gates reduced the BER to < 10⁻⁸ (near-perfect reliability) for CDC-XPUFs.
  • This performance significantly outperformed traditional majority voting techniques (e.g., 50x voting only achieved ~0.6% BER).

• Security Against ML Attacks:

  • Configurations with 10 components and 8 stages resisted all ML modeling attacks (using Neural Networks and Logistic Regression) even with training sets up to 200 million CRPs.
  • The attack success rate remained below the 90% threshold required for a "break," whereas traditional designs with fewer components were broken with fewer CRPs.

• Hardware Efficiency:

  • Gate Equivalents (GE): The lightweight 10-component/8-stage CDC-XPUF required only 1,368 GE, compared to 9,292 GE for a traditional 64-stage XOR-PUF.
  • Transmission Overhead: The design reduced transmission bits from 64 bits (standard) to 80 bits for the 10-component design, while maintaining a massive CRP space ($2^{80}$).
  • CRP Space: The 10-component/8-stage design supports a CRP space of $2^{80}$, vastly superior to the $2^{64}$ space of a standard 64-stage XOR-PUF.

5. Significance

This paper challenges the prevailing notion that traditional XOR-PUF architectures are inherently flawed and must be discarded. Instead, it demonstrates that:

• Refinement over Replacement: Existing PUF frameworks can be revitalized through strategic modifications (pre-selection and architectural re-balancing) rather than inventing entirely new, unproven structures.
• IoT Viability: The proposed Short-Stage CDC-XPUF offers a practical, deployable solution for resource-constrained IoT devices, solving the "trilemma" of Security (ML resistance), Reliability (noise immunity), and Efficiency (low cost/power).
• Attack Surface Reduction: By fundamentally removing response variability through hardware filtering, the design renders reliability-based side-channel attacks ineffective, a critical advancement for long-term IoT security.

In conclusion, the study provides a blueprint for sustainable PUF development, proving that incremental innovation on established designs can yield superior results for modern security landscapes.