Omnidirectional shuttling to avoid valley excitations in Si/SiGe quantum wells

1. Problem Statement

The paper addresses a critical bottleneck in scaling silicon-based quantum computers using electron-spin qubits in quantum dots: valley-state excitations during long-distance electron shuttling.

• Context: Conveyor-mode shuttling is a promising method for transporting qubits between quantum dots to enable intermediate-range coupling. However, in Si/SiGe heterostructures, the conduction-band valley splitting ($E_v$) is highly sensitive to atomic-scale disorder in the random SiGe alloy.
• The Challenge: Long shuttling trajectories inevitably encounter regions where the valley splitting drops to dangerously low levels. At these "valley-splitting minima," the electron is prone to Landau-Zener transitions, causing it to jump from the computational ground state (valley $|z-\rangle$) to an excited valley state ($|z+\rangle$). This results in leakage errors and loss of quantum information.
• Limitation of Current Tech: Conventional shuttlers are one-dimensional (1D). While strategies exist to detour around low-$E_v$ regions, 1D devices typically allow only small transverse shifts ($\Delta y \approx 20$ nm), which is insufficient to bypass the disorder features (requiring $\Delta y \gtrsim 100$ nm) to maintain high fidelity.

2. Methodology

The authors propose and theoretically analyze two new architectures designed to enable 2D motion, allowing electrons to detour around low-valley-splitting regions. They utilize numerical simulations based on a four-level (multichannel) and ten-level (2D) Hamiltonian model, incorporating random-alloy disorder statistics.

A. Multichannel Shuttling Scheme

• Design: Extends the conventional 1D shuttler by introducing parallel channels separated by screening gates.
• Mechanism: Electrons can tunnel between adjacent channels. By controlling the detuning ($\epsilon$) and tunnel coupling ($t_c$) via screening gates, an electron can transfer from one channel to another, effectively achieving a large transverse shift ($\Delta y \gtrsim 100$ nm).
• Protocols Simulated:
  1. "Paused" Protocol: The longitudinal motion stops while the electron tunnels between channels.
  2. "Moving" Protocol: The electron tunnels between channels while continuing to move longitudinally.
• Simulation: Modeled as a four-level system (two channels $\times$ two valley states). Disorder is modeled as uncorrelated random variables for valley splitting and phase in each channel.

B. Fully 2D Shuttling Scheme

• Design: A tiled array of "clavette" gates forming a 2D unit cell.
• Mechanism: By applying sinusoidally varying voltage signals with specific phase shifts to the 2D gate array, a moving potential pocket is created that can transport electrons in any arbitrary direction (omnidirectional).
• Protocols Simulated:
  • Trajectories can be programmed to detour around specific defects (e.g., semicircular paths).
  • Simulations focus on inter-pocket tunneling (leakage to neighboring potential pockets) and orbital excitations as the primary fidelity limits, assuming the path avoids valley minima.
• Simulation: Modeled as a 10-level system (5 pockets $\times$ 2 valley states) using a Lindblad master equation to account for coherent tunneling and phonon-mediated relaxation.

3. Key Contributions

1. Proposal of 2D Architectures: The paper introduces two specific hardware architectures (Multichannel and 2D Clavette) capable of providing the $\sim 100$ nm transverse shifts necessary to avoid valley-splitting minima.
2. Fidelity Analysis of Multichannel Shuttling:
   • Demonstrated that the "paused" protocol can achieve high success rates ($>95\%$) but suffers from scalability issues (all electrons must pause simultaneously).
   • Showed that the "moving" protocol is more scalable but suffers from significantly lower fidelity due to dynamic disorder and the inability to perfectly adiabatically follow the changing valley landscape during motion.
3. Validation of 2D Shuttling:
   • Proved that 2D shuttling can suppress inter-pocket leakage to negligible levels ($<10^{-9}$) by optimizing gate pitch ($P$) and voltage amplitude ($V_{amp}$).
   • Identified a "high-fidelity operating window" where orbital excitations are suppressed ($E_{orb} > 1.5$ meV) and inter-pocket tunneling is negligible ($t_p < 10^{-5}$ meV).
4. Scalable Architecture Proposal: Proposed a modular quantum computing architecture where "qubit plaquettes" are connected via 2D quantum interconnects, enabling all-to-all connectivity within plaquettes and high-fidelity communication between them.

4. Key Results

• Multichannel Performance:
  • In the paused regime, success probabilities exceed 95% for detuning $\epsilon_0 \in [500, 1000]$ $\mu$eV and tunnel coupling $t_0 \in [50, 150]$ $\mu$eV.
  • In the moving regime, success probabilities drop significantly (to $\sim 90\%$ or lower) as velocity increases, due to the difficulty of avoiding valley excitations dynamically.
• 2D Shuttling Performance:
  • Leakage out of the central pocket due to inter-pocket tunneling is extremely low ($1-F \approx 10^{-9}$) for typical parameters ($V_{amp} = 100$ mV, $P = 50$ nm).
  • The system allows for omnidirectional control, enabling the electron to navigate complex paths (e.g., detours) to avoid regions of low valley splitting.
  • The required wiring complexity is manageable (e.g., 16 control lines for a $4\times4$ unit cell).
• Architecture Viability: The proposed 2D architecture solves the "wiring fanout" and "connectivity" problems of spin qubits, allowing for nearest-neighbor gates to be extended to all-to-all connectivity via shuttling.

5. Significance

• Overcoming Material Disorder: The paper provides a concrete theoretical pathway to overcome the fundamental limitation of random-alloy disorder in Si/SiGe, which has previously threatened the scalability of spin-qubit shuttling.
• Enabling Large-Scale Quantum Computing: By enabling high-fidelity, long-distance transport of qubits, this work supports the transition from small-scale qubit arrays to large-scale, modular quantum processors.
• Practical Implementation: The 2D scheme relies on fabrication techniques (etched deposition, vertical vias) that are already being adopted in industrial settings, making the proposed architecture feasible for near-future implementation.
• Error Correction: The ability to achieve high-fidelity shuttling and all-to-all connectivity is crucial for implementing quantum error correction codes, which require high connectivity and low error rates.

In conclusion, the authors demonstrate that moving from 1D to 2D shuttling architectures is not just an incremental improvement but a necessary evolution to achieve the transverse maneuverability required to avoid valley excitations, thereby unlocking the potential for scalable, fault-tolerant silicon quantum computing.