On-chip stencil lithography for superconducting qubits

1. Problem Statement

The development of high-coherence superconducting qubits is currently limited by fabrication-induced losses, particularly from organic photoresists used in standard lithography.

• Resist Limitations: Organic resists used for shadow evaporation (the standard method for creating Josephson Junctions, or JJs) suffer from poor thermal stability (typically failing above ~300°C) and chemical incompatibility. They prevent the use of aggressive cleaning agents (like Piranha solution or hydrofluoric acid) and high-temperature annealing required to remove surface contaminants and two-level systems (TLS).
• Residue Issues: Resist residues, often called the "veil of death," and amorphous/poly-crystalline layers formed due to low-temperature processing degrade qubit coherence.
• Existing Alternatives: While off-chip stencil lithography (using free-standing membranes) exists, it suffers from alignment sensitivity, tilt issues, and mechanical stress at high temperatures, limiting scalability and reproducibility.

2. Methodology

The authors developed an inorganic on-chip stencil lithography technique using a Silicon Dioxide/Silicon Nitride ($SiO_2/Si_3N_4$) bilayer stack on sapphire substrates.

• Mask Fabrication:
  • A 300 nm sacrificial $SiO_2$ layer and a 100 nm $Si_3N_4$ mask layer are deposited via Low-Pressure Chemical Vapor Deposition (LPCVD) on a sapphire wafer.
  • The $Si_3N_4$ is patterned using standard electron-beam lithography (e-beam) and Reactive Ion Etching (RIE).
  • Resist Removal: Crucially, the organic resist is removed before the stencil is released. The wafer undergoes solvent cleaning, $O_2$ plasma ashing, and a Piranha solution dip. Because the $SiO_2$ sacrificial layer is still intact, the sapphire surface never contacts the resist, ensuring a pristine interface.
  • Stencil Release: The $SiO_2$ is selectively etched using aqueous hydrofluoric acid (A-HF), creating an undercut that releases the $Si_3N_4$ stencil mask from the substrate.
• High-Temperature Processing: The released inorganic stencil mask is robust enough to withstand temperatures up to 1200°C in Ultra-High Vacuum (UHV), allowing for aggressive surface cleaning and annealing prior to metal deposition.
• Deposition: Standard double-angle shadow evaporation is used to deposit Aluminum (Al) electrodes and form the Al/AlOx/Al Josephson Junctions through the stencil apertures.
• Mask Lift-off: Unlike resist-based lift-off, the inorganic mask is removed after deposition using Vapor Hydrofluoric Acid (V-HF).
  • The V-HF selectively etches the $SiO_2$ sacrificial layer but is stopped by the native Aluminum Oxide (AlOx) tunnel barrier of the JJ, protecting the functional device.
  • To facilitate this, the stencil design includes a hexagonal grid of small holes (~150 nm) that allow V-HF gas to penetrate and etch the underlying $SiO_2$ isotropically, causing the mask to detach.

3. Key Contributions

• First Application to Qubits: This is the first demonstration of on-chip stencil lithography applied to coherent superconducting quantum devices (transmon qubits).
• Resist-Free Interface: The process eliminates organic resist residues from the critical substrate-junction interface by removing the resist before the stencil is released.
• Thermal and Chemical Robustness: The method enables high-temperature annealing (up to 1200°C) and aggressive chemical cleaning (Piranha, HF) that are impossible with organic resists.
• Selective Lift-off Mechanism: The authors demonstrated a reliable lift-off technique using V-HF that exploits the chemical selectivity between $SiO_2$ and AlOx, ensuring the functional superconducting circuit remains intact.

4. Results

The team fabricated tunable transmon qubits (Q1 and Q2) on a single chip and characterized their coherence:

• Coherence Times:
  • Q1: Achieved an average energy relaxation time ($T_1$) of $75.37 \pm 7.42$ µs over a 60-hour period. The $T_1$ remained stable across a 200 MHz frequency range. The Ramsey dephasing time ($T_2^*$) was $\approx 15$ µs, and the echo time ($T_2^{echo}$) was $\approx 28$ µs.
  • Q2: Achieved an average $T_1$ of $44.28 \pm 8.23$ µs.
• Performance Comparison: The coherence times are comparable to state-of-the-art qubits fabricated using traditional resist-based methods, proving that the stencil process does not introduce additional decoherence sources.
• Stability: The qubits showed stable spectral purity and flux tunability, with no signs of degradation from the V-HF lift-off process.
• Material Quality: Scanning Electron Microscopy (SEM) and Transmission Electron Microscopy (TEM) confirmed sharp interfaces and the absence of fluorine contamination in the junction after V-HF exposure.

5. Significance and Outlook

• Overcoming the Decoherence Bottleneck: By enabling high-temperature processing and aggressive cleaning, this technique opens the door to exploring new junction materials and surface treatments that were previously inaccessible due to resist limitations.
• Scalability: The on-chip approach avoids the alignment and mechanical stability issues of off-chip stencils, offering a more reproducible path for scaling qubit fabrication.
• Future Potential: The authors suggest that leveraging the thermal robustness of this method could lead to further improvements in qubit performance, potentially pushing coherence times beyond current limits by eliminating TLSs at the substrate interface.

In conclusion, this work validates on-chip inorganic stencil lithography as a viable, high-performance alternative to organic resist lithography for superconducting quantum circuits, offering a pathway to cleaner interfaces and more robust qubit fabrication.