MOSAIX Qualification System for ALICE ITS3

This paper presents the development and verification strategy of the MOSAIX qualification system, which utilizes an FPGA-based test infrastructure and emulator to validate the testing environment for the wafer-scale MAPS prototype intended for the ALICE ITS3 upgrade prior to chip production.

The Gist

Imagine you are building a massive, ultra-thin, self-supporting tent for a high-stakes science experiment. This tent, called ITS3, is designed to track tiny particles zipping through the Large Hadron Collider. To make the tent as light as possible (so it doesn't get in the way of the particles), the builders are using a revolutionary new material: giant, flexible sheets of silicon sensors.

The star of this show is a specific chip called MOSAIX. It's not just a small sensor; it's a "System-on-Chip" that is 266 millimeters long—basically a whole factory of sensors stitched together onto a single piece of silicon.

Here is the problem: MOSAIX is incredibly complex. It's like a city with 144 different neighborhoods (called "tiles"), each with its own power grid, traffic lights, and data highways. All these neighborhoods are connected to a central hub. If one neighborhood has a power issue, or if the data highway gets clogged, the whole city stops working.

The Challenge: Testing Before You Build
Usually, when engineers build a complex machine, they test the individual parts first. But with MOSAIX, you can't test the parts separately because they are all fused together on one giant chip. You have to test the entire city at once.

Even worse, the chip wasn't ready yet. The team needed to write the software and build the testing equipment before the actual silicon chips arrived. If they waited for the chips to arrive to start testing, they would have wasted months of time.

The Solution: The "Digital Twin" (The Emulator)
To solve this, the team built a MOSAIX Emulator. Think of this as a hyper-realistic video game simulation of the chip.

• The Real Thing: The actual MOSAIX chip (which didn't exist yet).
• The Emulator: A powerful computer chip (an FPGA) that acts exactly like the real MOSAIX. It mimics the 144 neighborhoods, the power switches, and the data highways.

The team used this "Digital Twin" to do all the hard work early:

1. Training: Over 50 engineers learned how to operate the system on the simulator months before the real chip arrived.
2. Debugging: They discovered that the real chip has very strict rules about how to turn it on (you can't just flip a master switch; you have to turn on specific neighborhoods in a specific order). They found these tricky rules on the simulator, which would have taken months to figure out if they only had the real chip.
3. System Check: They built the physical testing equipment (the "control room") and connected it to the simulator to make sure everything worked together perfectly.

The Result: "Day-One Readiness"
Because they used the emulator, the team achieved something called "day-one readiness." This means that as soon as the first real MOSAIX chips arrive (expected in early 2026), the team won't need to spend time figuring out how to test them. They will be able to start testing immediately.

In Summary
The paper describes how the ALICE collaboration built a sophisticated testing system for a giant, complex sensor chip. Instead of waiting for the real chip to arrive to start learning how to test it, they built a perfect digital copy (the emulator) to practice on. This allowed them to find bugs, train their team, and build their tools in advance, ensuring that when the real "city" of sensors is finally delivered, they are ready to inspect it immediately.

Technical Summary

Technical Summary: MOSAIX Qualification System for ALICE ITS3

Problem Statement
The ALICE Inner Tracking System upgrade for LHC Run 4 (ITS3) introduces a novel detector architecture utilizing stitched, wafer-scale Monolithic Active Pixel Sensors (MAPS) to achieve an unprecedented material budget of 0.09% $X/X_0$ per layer. The core component, MOSAIX, is a 266 mm long, wafer-scale System-on-Chip (SoC) integrating 144 independently powered pixel tiles, complex power distribution networks, and high-speed data aggregation.

The primary challenge addressed by this paper is the qualification of MOSAIX. Unlike traditional sensors where components can be pre-tested, MOSAIX's high level of integration means individual components (such as the 144 tiles, 48 service nodes, and stitched backbone) cannot be tested in isolation before integration. The system requires a complex, sequential power-up and control strategy where the functionality of the entire service layer is a prerequisite for accessing individual pixel matrices. Furthermore, the need to determine yield and performance before dicing wafers into final detector layers necessitates a robust testing infrastructure that is ready immediately upon silicon availability ("day-one readiness").

Methodology and System Architecture
To address these challenges, the authors developed a unified qualification system centered on a "one system, many targets" philosophy. The hardware architecture consists of:

• Control Core: An Intel Arria 10 FPGA system-on-module mounted on an Enclustra baseboard, providing control and data acquisition.
• Interface: A standardized FMC connector on the readout board allows the same core system to interface with MOSAIX across various stages: custom probe cards for wafer-level testing, dedicated carrier boards for diced chips (enabling specific measurements like IR-drop along the sensor's z-axis), and the final Qualification Model of the ITS3 detector.
• Software Stack: A hardware-agnostic C++ API abstracts low-level FPGA interactions. Test sequences are separated from the core API in a standalone repository to facilitate community contribution and prevent accidental modification of critical procedures. The FPGA firmware was rigorously verified using a UVM-based environment and continuous integration (CI) regression testing.

The MOSAIX Emulator
A central methodological contribution is the development of a high-fidelity FPGA-based MOSAIX emulator. Developed over a year prior to the MOSAIX tapeout, this emulator addresses the risk of delayed discovery of integration issues.

• Implementation: Built on an identical Arria 10 platform, the emulator connects directly to the test system backend. It utilizes true RTL copies for control and data path logic, while employing lightweight behavioral models for pixel matrix readout.
• Functionality: Crucially, the emulator incorporates power- and state-aware modeling. It enforces correct operational sequences (e.g., refusing commands to tiles with "off" power switches), thereby forcing the control software to manage the complex dependencies of the real chip.
• Development Flow: A semi-automated CI flow managed the "moving target" nature of the MOSAIX RTL design, converting SystemRDL and RTL updates into FPGA formats with debug features, ensuring the emulator remained synchronized with the latest documentation.

Key Contributions and Results
The paper presents the completed foundational infrastructure for the MOSAIX qualification campaign. Key outcomes include:

1. Validated Infrastructure: The hardware, firmware, and core software API have been fully tested and validated against the FPGA emulator. Primary testing sequences are operational on the full setup.
2. Early Integration Verification: The emulator successfully served as a real-time application environment, uncovering operational complexities (such as the strict dependency of the service layer on global digital supply activation) that would have caused significant delays if discovered only after silicon delivery.
3. Training and Readiness: The emulator has functioned as a training tool, allowing over 50 users to gain hands-on experience with the chip months before its physical arrival.
4. Strategic Alignment: The system is designed to support the specific qualification goals: verifying chip features, estimating production yield, identifying a viable pixel variant, and qualifying the eight 10 Gb/s high-speed links to inform dicing strategies.

Significance
The paper asserts that the primary significance of this work lies in the value of early system integration enabled by the high-fidelity emulator. By decoupling the development of the test infrastructure from the availability of the physical silicon, the collaboration has effectively mitigated the risks associated with the chip's operational complexity and the scale of software development required.

With the first MOSAIX wafers expected in early 2026, the qualification system is positioned to begin the characterization campaign immediately. This "day-one readiness" is critical for providing necessary design feedback by mid-2026, ensuring the ALICE ITS3 upgrade remains on schedule. The paper concludes that the emulator approach was essential in managing the intricate dependencies between the chip's subsystems and validating the testing strategy before the final prototype was available.