Advancements and future expansions of the Caribou DAQ system

This paper outlines recent advancements and future prospects of the Caribou DAQ system, detailing hardware, firmware, and software developments that prepare the versatile platform for its upcoming transition to version 2.0 based on a Zynq UltraScale+ architecture.

The Gist

Imagine you are a master chef trying to test a brand-new, incredibly delicate type of oven (a silicon pixel detector). To see if it works, you need a control panel that can turn the heat on and off, measure the temperature with extreme precision, and send signals to the oven to see how it reacts.

In the world of particle physics, scientists need to test thousands of these "ovens" before they can be used in giant experiments like those at CERN. The Caribou system is the ultimate "universal control panel" built to do exactly this.

Here is a simple breakdown of the paper, using everyday analogies:

1. The Current Setup: The "Swiss Army Knife" (Caribou v1)

Right now, scientists use Caribou v1. Think of this as a high-tech Swiss Army Knife.

• The Handle (The SoC): It has a brain (a Xilinx Zynq chip) running a smart operating system.
• The Tools (The CaR Board): Attached to the handle is a custom board (the Control and Readout board) that holds all the tools: power supplies, voltage meters, and signal injectors.
• The Software (Peary & Boreal):
  • Peary is like the user manual and remote control. It lets scientists talk to the hardware using simple commands or Python code.
  • Boreal is like the instruction manual for building the tools. It provides pre-made, reusable parts so engineers don't have to reinvent the wheel every time they test a new detector.

This system is great because it's flexible. You can swap out the "blade" (the detector) without changing the "handle" (the main computer).

2. The Problem: The Knife is Getting Dull

While the current system works well, the scientists are building Caribou v2.0, and they need to upgrade the "tools" because the detectors they are testing are becoming more complex and demanding.

• The Old Power: The current power supplies are like a dimmer switch that only goes from 0 to 10. The new detectors need a switch that goes from 0 to 100, with much finer control.
• The Old Meters: The current voltage meters are good, but the new detectors need "microscopes" to see tiny electrical changes.
• The Old Brain: The current computer chip is getting a bit old. The new system needs a faster, more powerful brain (an UltraScale+ chip) to handle more data.

3. The Upgrade: Building a "Pro-Grade" Control Center (Caribou v2)

The paper describes the massive effort to build Caribou v2.0. Here is what is changing:

• Super-Powered Supplies: The new board will have power sources that can handle much higher voltages and currents, with incredibly precise steps (like being able to turn a dial by just a tiny fraction of a degree).
• Better Meters: They are replacing the old "ruler" with a "laser measure" (a 24-bit ADC) to get ultra-precise readings.
• Modular Design: Instead of having everything built-in, the new board will have a slot (an FMC connector) where you can plug in different "add-on" cards depending on what you need for the day. It's like upgrading from a fixed kitchen counter to one with a plug-in station for a blender, a toaster, or a mixer.

4. The "Test Kitchen" (Validation)

Before they build the final version, they built a simplified test board (shown in Figure 2b of the paper).

• The Analogy: Imagine you are building a new, complex car engine. Before you put it in a Ferrari, you build a small, stripped-down version of the engine on a workbench. You test the pistons, the fuel injectors, and the cooling system one by one.
• The Result: They built two of these test boards. They tested the power supplies, the current limits, and the safety features. Everything is working perfectly, proving that the design for the final "Caribou v2" is solid.

5. The New "Brain" (Software Redesign)

The hardware is only half the story. The software (Peary) was completely rewritten.

• The Old Way: The software was written specifically for one type of computer chip. If you changed the chip, the software broke.
• The New Way (The HAL): The new software uses a Hardware Abstraction Layer (HAL).
  • Analogy: Think of this like a universal translator. Instead of the software talking directly to the specific wires and chips, it talks to a "Resource" (like "Voltage Source"). The translator then figures out how to talk to the specific hardware underneath.
  • Benefit: Now, if you swap the computer chip or change the board, the software doesn't need to be rewritten. It just asks the translator, "How do I turn on the voltage?" and the translator handles the rest. This makes the system future-proof.

6. The "Lego" Blocks (Firmware)

The paper also mentions Boreal Modules.

• The Analogy: Imagine you are building with Lego. Instead of every builder making their own unique bricks from scratch, there is a central warehouse of standardized, high-quality Lego bricks (counters, timers, data links).
• The Goal: Scientists can grab these pre-made, tested "bricks" and snap them together to build their specific detector logic. This saves time and ensures everything fits together perfectly.

Summary: Why Does This Matter?

This paper is essentially a progress report on upgrading the universal remote control for the next generation of particle detectors.

By upgrading the power supplies, sensors, and software architecture, the Caribou team is ensuring that when the next big physics experiment happens, the scientists will have a reliable, flexible, and powerful tool to test their detectors quickly and accurately. It's about moving from a "good enough" tool to a "professional-grade" tool that can handle whatever the future of physics throws at it.

Technical Summary

1. Problem Statement

The development of novel silicon pixel detectors for high-energy physics experiments requires Data Acquisition (DAQ) systems that are highly versatile, reusable, and capable of supporting rapid prototyping, laboratory qualification, and test-beam operations. While the existing Caribou system (Version 1.0) successfully addressed these needs using a Xilinx Zynq SoC and a custom Control and Readout (CaR) board, it faces limitations as detector requirements evolve. Specifically:

• Hardware Limitations: The v1 architecture relies on 12-bit DACs with limited voltage/current ranges (e.g., a restricted 1.024 mA current range) and lacks the flexibility to support high-voltage supplies or high-precision monitoring required by next-generation detectors.
• Software Rigidity: The embedded software (Peary) was originally centered around the ZC706 platform, making it difficult to scale to newer SoC architectures (like UltraScale+) or integrate diverse CaR board revisions without significant reconfiguration.
• Scalability: There is a need for a more modular framework to support a growing number of detector prototypes and diverse hardware platforms within a unified environment.

2. Methodology

The authors adopted a holistic approach to evolve the Caribou ecosystem, targeting a transition to Version 2.0 based on a Zynq UltraScale+ System-on-Module (SoM) architecture. The methodology involved parallel advancements in three key domains:

• Hardware Validation and Design:

  • Developed a dedicated validation setup for CaR v1 using a Zynq board, adapter board, and custom breakout board to verify LVDS lines, transceiver links, power supplies, and ADCs before user distribution.
  • Designed a simplified v2 test board (16.5 × 17.5 cm²) to evaluate new analog components (high-voltage supplies, bipolar current sources, 16-bit DACs) via a USB-to-I2C/SPI interface, excluding the SoM during the initial phase.
  • Planned the removal of the integrated low-speed monitoring ADC in v2 in favor of an FMC connector for flexible high-speed ADC expansion.

• Firmware Infrastructure (Boreal):

  • Established the Boreal Modules project to centralize the development of common soft Intellectual Property (IP) cores.
  • Implemented a flexible verification workflow using Cocotb (coroutine-based co-simulation) while allowing toolchain choice.
  • Focused on migrating existing logic (counters, AXI4-Lite maps, Trigger Logic Units) from ZC706 to UltraScale+ platforms (ZCU102, Mercury+).

• Software Architecture Revision (Peary):

  • Executed a complete redesign of the Peary C++ embedded DAQ application.
  • Introduced a Hardware Abstraction Layer (HAL) based on the concept of "Resources." In this model, logical functionalities (e.g., setting voltage, monitoring current) are treated as Resources composed of multiple hardware components.
  • Restructured the system into four functional spaces: HAL (Resources), System Interface (I²C, SPI, serial links), DAQ Library (configuration, logging, device management), and Command Line Interface (CLI).

3. Key Contributions

• Next-Generation Hardware Architecture (CaR v2):

  • Enhanced Power/Bias Control: Transition from 12-bit to 16-bit multi-range DACs for bias generation, supporting ±15V bipolar outputs.
  • Advanced Current Sources: Introduction of selectable bipolar ranges spanning from tens of microamperes (step size 10 nA) up to ~100 mA (step size 50 µA), a significant improvement over v1's 1.024 mA limit.
  • Precision Monitoring: Replacement of low-speed ADCs with 24-bit high-resolution ADCs for precision measurements.
  • Modularity: Integration of FMC connectors to support external high-speed ADC cards and FPGA-based overcurrent protection.

• Unified Firmware Framework (Boreal Modules):

  • Creation of a shared repository for reusable IP cores (counters, edge detectors, synchronization logic) with automated build workflows, ensuring consistency across different projects and platforms.

• Modular Software Framework (Peary v2):

  • Decoupling of hardware specifics from application logic via the Resource-based HAL. This allows the software to support any combination of CaR board and Zynq platform without rewriting core logic.
  • Standardized interfaces for device lifecycle management and automated detector qualification routines via Python and CLI.

4. Results

• Hardware Validation:
  • The CaR v1 validation setup successfully verified LVDS lines, power supplies, and ADCs, establishing a robust pre-deployment testing routine.
  • The CaR v2 test board is fully operational. Key performance metrics achieved include:
    • HV Supplies: Adjustable outputs from ±2.5V to ±18V at up to 1A.
    • Current Sources: Gain error performance within ±0.1–0.25% of full-scale range.
    • Bias Source: ±15V output with programmable current limits (±10.24 mA).
    • Protection: FPGA-based current protection logic successfully tested, allowing configurable limits and group fault handling.
• Software & Firmware:
  • The new Peary architecture has been successfully tested, demonstrating the ability to abstract hardware resources and manage devices across different platforms.
  • Boreal Modules are actively expanding, with logic IPs being adapted for UltraScale+ compatibility.

5. Significance

This work represents a critical evolution in the infrastructure supporting high-energy physics detector R&D.

• Scalability and Future-Proofing: By transitioning to the UltraScale+ SoM and adopting a resource-based software architecture, Caribou is positioned to support detector technologies for decades, accommodating future high-voltage and high-precision requirements.
• Efficiency: The modular design reduces the time-to-deployment for new detector prototypes. Researchers can integrate new hardware with minimal software reconfiguration, and the shared firmware/software stacks prevent code duplication across the 14+ institutes using the system.
• Precision and Reliability: The enhanced analog capabilities (16-bit/24-bit resolution, bipolar ranges, FPGA protection) directly improve the quality of detector characterization data, enabling more accurate qualification of novel silicon pixel sensors.
• Collaborative Standardization: The project strengthens the collaboration between CERN, ORNL, BNL, DESY, and Carleton University, providing a unified, open-source ecosystem for detector control and readout.