FPGA-Based Real-Time Waveform Classification

This paper presents an FPGA-based real-time waveform classification system for SiPM signals that utilizes resource-efficient, genetic algorithm-trained binary neural networks to enable dead-time-free data reduction and reliable particle hit extraction.

The Gist

The Big Picture: The "Over-Worked Security Guard"

Imagine a particle physics experiment as a massive, high-security airport. Every second, thousands of "passengers" (particles) fly through the detectors. The sensors (SiPMs) act like security cameras, recording a video stream of every single person who walks by.

The Problem:
The security team (the computer system) is drowning.

1. Too much data: Recording every single video frame is impossible to store or send to the control room. It would clog the internet.
2. Too slow: The current security guards (standard computer chips) are smart, but they take too long to watch a video, decide if it's important, and file a report. By the time they finish, the next 1,000 passengers have already walked through, causing a traffic jam (called "dead time").

The Goal:
We need a security guard who can look at a person for a split second, instantly decide: "Is this a normal passenger? Is this a suspicious person needing a full search? Or is this just a bird flying past the camera?" and then immediately let the next person through without stopping.

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The Solution: The "Binary Brain" on a Chip

The authors propose building a special kind of "brain" (a Neural Network) directly onto a programmable chip (an FPGA). But they realized that standard AI brains are too heavy and slow for this job. So, they built a Binary Neural Network (BNN).

1. The "On/Off" Switch Analogy

Standard AI brains work like a dimmer switch. They use complex math with numbers like 3.14159 or 0.007 to make decisions. This requires heavy machinery (DSPs and BRAMs) inside the chip, which is slow and takes up a lot of space.

The authors' new brain works like a simple light switch. It only understands two states: ON (1) and OFF (0).

• Instead of doing complex multiplication, the chip just looks up the answer in a pre-made list (a Look-Up Table or LUT).
• The Analogy: Imagine a standard chef trying to bake a cake by measuring flour to the exact milligram (slow, requires scales). The new approach is like a chef who only has two recipes: "Make Cake" or "Don't Make Cake." They just flip a switch, and the cake appears instantly.

2. The "Genetic Evolution" Training

Usually, you teach an AI by showing it thousands of examples and correcting its mistakes using math (back-propagation). But because this new "light switch" brain is so simple and rigid, you can't use standard math to correct it. It's like trying to teach a robot to walk by pushing it; if the robot only has two legs, pushing it doesn't help it learn to balance.

The Solution: They used a Genetic Algorithm (GA).

• The Analogy: Imagine you are breeding a super-fast racehorse.
  1. You start with 1,000 random horses (randomly wired brains).
  2. You race them. Some stumble, some run fast.
  3. You take the fastest horses, mix their DNA (swap their wiring), and give their babies a few random mutations (maybe one gets a slightly longer leg).
  4. You repeat this for hundreds of generations.
  5. Eventually, you have a horse that is perfectly evolved to run fast on this specific track.
• In the paper, the "horses" are the neural networks, and the "race" is identifying particle signals. The computer evolved a network that is perfectly wired for the specific chip it lives on.

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The Results: Speed vs. Smarts

The authors tested their new "Binary Brain" against the standard "Dimmer Switch" brains (like FINN and hls4ml).

Feature	Standard AI (Dimmer Switch)	New Binary AI (Light Switch)
Speed	Takes about 24,000 nanoseconds (too slow for real-time).	Takes only 10–15 nanoseconds (blazing fast!).
Hardware	Needs heavy, expensive parts (DSPs).	Uses only simple logic gates (LUTs).
Accuracy	Very high (95%+).	Good, but lower (64–74%).
Verdict	Great for offline analysis, but causes traffic jams.	Perfect for real-time filtering. It's fast enough to let the traffic flow freely.

Why is the lower accuracy okay?
In this specific job, the AI doesn't need to be perfect. It just needs to be fast enough to catch the "Good" signals and the "Ugly" (suspicious) signals. Even if it misses a few "Good" ones, it's better than having a traffic jam where nothing gets processed. The goal is to filter out the "Bad" (noise) instantly so the system doesn't waste time on garbage data.

The "Magic" Tool

The authors also built a translator tool (Python to VHDL). Think of it as a universal translator that takes the "DNA" of the evolved horse (the weights from the genetic algorithm) and automatically writes the blueprints for the chip. This means scientists can evolve a new brain in software and instantly print it onto hardware without needing to be an expert chip designer.

Summary

The paper presents a clever workaround for a speed problem in particle physics. Instead of trying to make the computer "smarter" (which makes it slower), they made it "dumber" (binary) but trained it using evolution (genetic algorithms) to be incredibly fast.

The Result: A system that can sort through a flood of particle data in the blink of an eye, ensuring the experiment never stops to catch its breath.

Technical Summary

1. Problem Statement

The paper addresses the challenge of processing high-rate data from Silicon Photomultiplier (SiPM) sensors in particle physics experiments.

• Data Volume: Raw waveform data from SiPMs is voluminous and expensive to transmit. Early data reduction is critical.
• Latency Constraints: Physics experiments often require "dead-time free" processing. For a specific example cited (100-sample window, 12-bit ADC, 800 MSamples/s), the maximum allowable processing time is 125 ns.
• Limitations of Current Solutions: Standard FPGA implementations of Artificial Neural Networks (ANNs) typically rely on clocked components like Digital Signal Processors (DSPs) and Block RAMs (BRAMs). These introduce significant latencies (often >2000 ns), making them unsuitable for real-time, dead-time-free triggering.
• Classification Task: The goal is to categorize SiPM signals into three classes:
  1. "Good": Standard signal shapes (parameterizable).
  2. "Ugly": Complex shapes (e.g., pile-up events) requiring full waveform analysis.
  3. "Bad": Irrelevant noise (to be discarded).

2. Methodology

The authors propose a novel hardware-constrained approach using Binary Neural Networks (BNNs) implemented entirely via combinatorial logic, avoiding clocked resources.

A. Network Architecture (Hardware-Constrained Design)

Instead of the standard "Quantization Aware Training" flow (FP $\to$ INT $\to$ HDL), the authors design the network directly for FPGA Look-Up Tables (LUTs):

• Neuron/Weight Precision: Hidden layers use 2-bit values for both neurons and weights.
• Input Handling: The first layer handles 12-bit integer inputs directly, avoiding slow normalization steps. Operations are constrained to four specific logic functions (Pass, Increment, Negation, Block) to fit within 4x4 CAMs (Content-Addressable Memories).
• Logic Implementation:
  • Multiplication is replaced by LUT operations.
  • Summation uses pairwise tree addition to optimize carry chains logarithmically.
  • Activation functions use thresholds to map integer sums back to 2-bit values (one-hot encoded).
• Intrinsic Pruning: A "Blocking" operation (output always 0) allows the network to prune connections intrinsically during training.

B. Training via Genetic Algorithms (GA)

Since the proposed architecture uses non-differentiable operations (LUTs, bit shifts), standard back-propagation cannot be used.

• Algorithm: The authors utilize a Genetic Algorithm (GA) (using the deap Python package) to evolve the network weights.
• Process:
  1. Population: A set of individuals (unique NN configurations) is generated.
  2. Fitness Evaluation: Individuals are tested against simulated SiPM signals ("Good" and "Ugly" waveforms). Fitness is based on classification accuracy, with a penalty for trivial classifiers (e.g., always predicting one class).
  3. Evolution: The next generation is created via selection, mutation (random weight changes), and crossover.
  4. Multi-objective Optimization: The GA maximizes accuracy while minimizing the number of non-zero weights (promoting smaller, more efficient networks).
• Output: The trained weights are converted directly into VHDL code via a custom Python-to-VHDL tool.

3. Key Contributions

1. Sub-20ns Latency Architecture: The design achieves inference latencies below 20 ns (specifically 10–15 ns in results), which is orders of magnitude faster than DSP/BRAM-based baselines. This fits comfortably within the 125 ns dead-time constraint.
2. Resource Efficiency: The solution utilizes zero DSPs and zero BRAMs, relying solely on LUTs and Flip-Flops (FFs). This drastically reduces the hardware footprint.
3. GA-Based Training for BNNs: Demonstrates the viability of training 2-bit binary networks using Genetic Algorithms specifically tailored for non-differentiable, LUT-based hardware constraints.
4. Open Toolchain: The authors provide a self-contained Python-to-VHDL conversion tool that translates trained weights directly into synthesizable FPGA code.

4. Results

The study compares two BNN configurations ($BNN_a$: 128-64-128-2 and $BNN_b$: 128-32-32-2) against baseline Convolutional Neural Networks (CNNs) implemented via FINN and hls4ml on a Xilinx ZCU104 device.

Metric	FINN (CNN)	hls4ml (CNN)	BNN$_a$	BNN$_b$
Accuracy	74 ± 4%	94.9%	64 ± 5%	74 ± 5%
Latency	~24,850 ns	~3,050 ns	15 ns	10 ns
LUTs	30k	186k	58k	23k
DSPs	20	112	0	0
BRAMs	106	556	0	0

• Performance Trade-off: While the BNNs show lower accuracy (64–74%) compared to the hls4ml baseline (94.9%), they achieve a ~200x to ~300x reduction in latency.
• Robustness: The BNNs correctly identified that random noise input did not classify as "Good" or "Ugly," demonstrating robust noise rejection.
• Scalability: The smaller network ($BNN_b$) achieved similar accuracy to the larger one ($BNN_a$) with significantly fewer resources (23k LUTs vs 58k) and lower latency (10 ns vs 15 ns).

5. Significance and Outlook

• Real-Time Viability: This work proves that complex waveform classification can be performed in real-time on FPGAs without incurring dead time, a critical requirement for high-luminosity particle physics experiments.
• Paradigm Shift: It challenges the reliance on DSPs for edge AI in physics, showing that combinatorial logic (LUTs) is sufficient for specific, latency-critical tasks.
• Future Improvements:
  • Segment-wise Evaluation: To overcome BRAM access bottlenecks, the authors suggest evaluating waveform segments with simpler networks to make decisions before the full frame is received.
  • Hybrid Training: Incorporating gradient-based correction steps into the GA mutation process to blend the exploration of GAs with the efficiency of gradient descent.

In conclusion, the paper presents a highly efficient, ultra-low-latency solution for online particle data filtering, trading a moderate reduction in classification accuracy for a massive gain in processing speed and hardware resource efficiency.