Large Language Model for Verilog Code Generation: Literature Review and the Road Ahead
This paper presents a comprehensive systematic literature review of 102 studies on using Large Language Models for Verilog code generation, analyzing current methods, datasets, and alignment strategies while identifying limitations and proposing a future research roadmap to advance automated hardware design.
Original paper licensed under CC BY 4.0 (http://creativecommons.org/licenses/by/4.0/). This is an AI-generated explanation of the paper below. It is not written or endorsed by the authors. For technical accuracy, refer to the original paper. Read full disclaimer
Imagine a world where the blueprints for the most complex machines on Earth are written not by human hands, but by a computer that reads and understands natural language. This is the frontier of electronic design, a field where engineers describe how silicon chips should behave using a specialized language called Verilog. For decades, this process has been a meticulous, human-heavy endeavor, requiring deep expertise to ensure that the resulting circuits function correctly, fit within physical space limits, and do not overheat. Recently, a new kind of artificial intelligence, known as a large language model, has begun to enter this arena. These models, which have already proven capable of writing software for computers, are now being tested to see if they can design hardware. The stakes are high: as chips become more intricate, the gap between human productivity and the demands of modern technology is widening, creating a bottleneck that threatens to slow down innovation in everything from smartphones to supercomputers.
A comprehensive review published in 2025 by a team of researchers from universities in China, Australia, and Singapore sets out to map this rapidly evolving landscape. The authors, led by Guang Yang and Wei Zheng, did not just look at a few recent experiments; they conducted a systematic search through thousands of academic papers and preprints to find every study that applied these powerful AI models to Verilog code generation. After a rigorous filtering process, they settled on 102 high-quality studies published between 2020 and 2025. Their goal was to understand what tools are being used, how well they are being tested, what techniques are improving their performance, and whether the resulting designs are safe and reliable enough for real-world use.
The researchers found that the field has exploded in just a few years, growing from a single study in 2020 to 66 papers in 2025 alone. They discovered that the AI models driving this progress come in two main flavors. The first group consists of general-purpose models, the same kinds that can write stories or answer questions, which researchers are trying to adapt for hardware design. The second group includes models that have been specifically trained or fine-tuned on vast amounts of Verilog code. Among the open-source models available to researchers, families based on the Llama and DeepSeek architectures have become the most popular choices, while closed-source models from major technology companies, particularly those in the GPT series, remain dominant in terms of raw usage. The review highlights a clear trend: while general models can produce code, the most promising results come from models that have been taught the specific rules and logic of hardware design.
To know if these AI-generated designs actually work, the researchers examined how scientists are testing them. They found that the field is moving away from simple checks that only look at whether the code looks like correct text. Instead, the most reliable studies now use "testbenches," which are automated simulations that run the generated code to see if it behaves exactly as intended. The review cataloged dozens of these testing datasets, noting that while many are still small, the best ones include thousands of examples with detailed instructions and verified solutions. A critical finding is that the quality of the data used to train these models is just as important as the model itself. Researchers are increasingly building datasets that not only contain code but also include the reasoning steps and the specific constraints of the hardware, teaching the AI to think like an engineer rather than just a text predictor.
The paper also details the methods researchers are using to make these models better. Some approaches do not require changing the model at all; instead, they use clever prompting techniques or ask the AI to check its own work against standard engineering tools before finalizing a design. Other methods involve training the models further on specialized data or using a technique called reinforcement learning, where the model is rewarded for producing code that passes rigorous tests and penalized for errors. The review suggests that combining these strategies, particularly by having multiple AI agents work together—one to design, one to check, and one to optimize—yields the best results. However, the authors caution that even with these improvements, the technology is not yet perfect. The models still struggle with the complex, parallel nature of hardware, sometimes producing code that looks right but fails when built.
Perhaps most importantly, the review addresses the risks associated with handing over design tasks to AI. The researchers analyzed how current studies handle security, efficiency, and copyright. They found that while some progress has been made in preventing the AI from generating code with hidden vulnerabilities or stealing intellectual property, these areas remain underdeveloped. The models can sometimes "hallucinate," creating plausible-sounding designs that contain logical errors which only appear when the chip is manufactured. The authors conclude that while large language models hold immense promise for transforming how we build hardware, the path forward requires more than just better code generation. It demands a new generation of benchmarks that test for physical constraints, stronger safety mechanisms, and tools that allow human engineers to collaborate closely with the AI. The future of this field, they suggest, lies not in replacing human designers, but in creating intelligent assistants that can handle the complexity of modern chips while keeping the human expert in the loop to ensure safety and reliability.
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