Review of prototypes developed in a 65 nm CMOS imaging technology in view of vertexing applications at a future lepton collider

This paper reviews the design, simulation, and performance of monolithic active pixel sensor prototypes developed in 65 nm CMOS technology for future lepton collider vertexing applications, concluding that the approach is feasible while highlighting remaining challenges and guiding future design decisions.

The Gist

Imagine you are trying to take a super-clear, high-speed photograph of a tiny, fast-moving firefly flying through a dark room. To do this, you need a camera that is incredibly thin, consumes very little battery power, can withstand being hit by dust storms, and can pinpoint exactly where the firefly was at any given nanosecond.

This paper is essentially a report card for a new type of camera sensor being developed for the world's most advanced particle physics experiments (specifically, future "lepton colliders" like the FCC-ee). These experiments smash particles together to understand the universe, and they need these "cameras" to track the paths of the resulting debris with extreme precision.

Here is the breakdown of the paper using simple analogies:

1. The Goal: The "OCTOPUS" Project

The researchers are working on a project called OCTOPUS. Their goal is to build a "Monolithic Active Pixel Sensor" (MAPS).

• The Old Way (Hybrid Detectors): Imagine a camera where the lens is glued onto a separate piece of glass containing the film. It's thick, heavy, and expensive to assemble.
• The New Way (MAPS): Imagine printing the lens and the film on the same piece of paper. It's thinner, lighter, cheaper, and uses less power.
• The Challenge: They are using a very advanced manufacturing process (65 nm CMOS, the same kind used in modern smartphones) but pushing it to the extreme limits required for particle physics.

2. The Three Designs: How to Catch the Charge

When a particle hits the sensor, it creates a tiny electrical charge (like a spark). The sensor needs to catch this spark and send it to a computer. The paper tests three different "floor plans" for how the sensor is built to catch these sparks:

• The Standard Layout (The Open Field): The easiest to build. The "catching net" (depletion region) is shaped like a balloon. However, the edges are a bit fuzzy, and sparks sometimes drift away before being caught.
• The N-Blanket Layout (The Full Net): They added a special layer to make the net cover the entire pixel area. This catches more sparks, but the net is a bit "sluggish" at the edges, so it takes longer to gather the charge.
• The N-Gap Layout (The Guided Slide): This is the star of the show. They put a small "gap" in the design that creates an invisible slide. If a spark is created near the edge, the slide gently pushes it quickly toward the center. This is the most efficient design for speed and accuracy.

3. The Results: How Well Do They Work?

The team tested many different prototypes (versions of the camera) with different pixel sizes (like the size of individual pixels on your phone screen).

• Precision (Spatial Resolution): They want to know exactly where the particle hit.
  • The Analogy: If you throw a dart at a board, how close can you get to the bullseye?
  • The Result: The sensors can pinpoint the location to within 3 micrometers (that's thinner than a human hair!). The "N-Gap" design works best, especially if the pixels are small (around 15 micrometers).
• Speed (Temporal Resolution): They need to know when the particle hit.
  • The Analogy: How fast can your camera shutter snap?
  • The Result: They are aiming for 5 nanoseconds. Some prototypes are already hitting this, but it depends heavily on the electronics inside the chip.
• Efficiency: Do they miss any particles?
  • The Result: Yes, they catch over 99% of particles, provided the "sensitivity threshold" (how loud the spark needs to be to be noticed) is set correctly.
• Power: The camera must be energy-efficient so it doesn't overheat the experiment.
  • The Result: They are getting close to the goal of using very little power, but it requires careful tuning of the electronics.

4. The "Radiation Hardness" Test

Particle colliders are radioactive environments. It's like asking your camera to survive inside a nuclear reactor.

• The Test: They zapped the sensors with high doses of radiation (neutrons and gamma rays).
• The Result: The sensors held up surprisingly well! Even after being hit by radiation equivalent to years of operation, the "N-Gap" design still worked almost as well as a new one. The other designs got a bit "noisy" (like a radio with static), but the N-Gap remained clear.

5. The Simulation: The "Virtual Prototype"

Before building the real chips, they used powerful computers to simulate how the sensors would behave.

• The Analogy: It's like using a flight simulator to test a new airplane design before building the real metal.
• The Result: The computer models matched the real-world tests very well. This proves they can trust their simulations to design the next generation of sensors without needing to build and test as many physical prototypes.

The Bottom Line

This paper is a "green light" for the future. It shows that using standard smartphone manufacturing technology (65 nm CMOS) to build ultra-precise particle trackers is feasible.

While there are still some engineering challenges to solve (like balancing power consumption with speed), the "N-Gap" design looks like the winner. If they can perfect this, future particle colliders will have "eyes" that are thinner, faster, and more durable than anything we have today, allowing us to see the building blocks of the universe with unprecedented clarity.

Technical Summary

1. Problem Statement

The High-Energy Physics (HEP) community is preparing for future lepton colliders (e.g., FCC-ee, ILC, CLIC), which require vertex and tracking detectors with unprecedented performance specifications. The OCTOPUS project aims to develop Monolithic Active Pixel Sensors (MAPS) using the TPSCo 65 nm ISC (CMOS Imaging Sensor) technology to meet these needs.

The specific design requirements for these sensors include:

• Spatial hit resolution: < 3 µm.
• Temporal hit resolution: ~5 ns.
• Material budget: Equivalent to ~50 µm of silicon (to minimize multiple Coulomb scattering).
• Power consumption: < 50 mW cm⁻².
• Radiation hardness: Tolerance to a neutron equivalent fluence of $O(10^{14} \text{ neq cm}^{-2})$ and a Total Ionizing Dose (TID) of $O(100 \text{ kGy})$ over a 4-year Z-pole operation.

The challenge lies in verifying if this specific commercial CMOS process, originally designed for imaging, can be adapted to meet these rigorous HEP requirements through sensor layout optimization and circuit design.

2. Methodology

The authors conducted a comprehensive review and synthesis of experimental data from a wide range of prototype chips produced in the TPSCo 65 nm technology. The methodology involved:

• Prototype Selection: Analysis of multiple chip submissions (MLR1 in 2020 and ER1 in 2023) including:
  • APTS (Analog Pixel Test Structure): 4x4 matrices with various pitches (10–25 µm) and layouts for analog characterization.
  • DPTS (Digital Pixel Test Structure): 32x32 matrices with Time-over-Threshold (ToT) readout.
  • CE65/CE65v2: Chips exploring different amplification schemes (SF, DC-coupled, AC-coupled) and layouts.
  • DESY-MLR1/ER1: Charge Sensitive Amplifier (CSA) test chips.
  • H2M (Hybrid-to-Monolithic): A 64x16 matrix ported from hybrid technology to test digital integration.
  • MOSS/MOST: Large-scale prototypes using reticle stitching for the ALICE ITS3 upgrade, featuring granular powering.
• Sensor Layouts: Evaluation of three primary pixel architectures:
  1. Standard: Depletion grows from the collection electrode; charge transport at boundaries is diffusion-dominated.
  2. N-blanket: A deep n-type implant extends depletion across the full pixel but lacks strong lateral fields.
  3. N-gap: A gap in the n-implant creates a lateral doping gradient and electric field, actively sweeping charge from boundaries to the center.
• Experimental Campaigns: Prototypes were tested at facilities like DESY II and CERN PS/SPS using beam telescopes (EUDET-type, ALPIDE-based) and radioactive sources ($^{90}\text{Sr}$, $^{55}\text{Fe}$).
• Simulation: The paper reviews simulation efforts using TCAD (Sentaurus, Silvaco) for electrostatics, Allpix2 and Garfield++ for Monte Carlo particle transport, and SPICE (Cadence, LTspice) for front-end electronics modeling. These tools were used to validate experimental results and predict performance for untested geometries.

3. Key Contributions

• Comprehensive Performance Review: The paper aggregates data from diverse prototypes to establish a baseline performance map for the 65 nm TPSCo technology, covering noise, efficiency, resolution, and power.
• Layout Comparison: It provides a systematic comparison of the Standard, N-blanket, and N-gap layouts, demonstrating that the N-gap layout offers the best compromise between charge collection efficiency and spatial resolution due to its lateral electric field.
• Radiation Hardness Assessment: It presents early data on the radiation tolerance of these sensors, identifying the N-gap layout as the most robust candidate for future collider environments.
• Simulation Validation: The work validates the use of technology-independent simulation chains (TCAD + Allpix2 + SPICE) to accurately predict sensor behavior, reducing the need for costly production cycles.

4. Key Results

General Properties

• Noise: Equivalent Noise Charge (ENC) ranges from 9 e⁻ to 36 e⁻, depending on the front-end design and bias voltage. The N-gap layout generally shows lower noise sensitivity to bias voltage changes compared to the standard layout.
• Power: Power consumption varies significantly. The DPTS matrix consumes 12–120 nW per pixel (5.3–53 mW cm⁻²), meeting the <50 mW cm⁻² target if optimized. MOSS analog power density is reported at 7–11 mW cm⁻².
• Threshold: Operational thresholds typically range between 100 e⁻ and 200 e⁻. The N-gap layout achieves a 99% hit-detection efficiency ($T_{99}$) at thresholds of 147–221 e⁻, outperforming the standard layout (88–152 e⁻).

Charged Particle Detection

• Spatial Resolution:
  • For a 15 µm pitch, the N-gap layout achieves a binary resolution ($\sigma_{bin}$) of ~3.1 µm.
  • Using charge information (charge-weighted interpolation), the Standard layout can achieve resolutions as low as ~1.4 µm (at 15 µm pitch), while N-gap remains around 3.1 µm.
  • To meet the <3 µm requirement, the N-gap layout requires a pitch < 15 µm, whereas the Standard layout can tolerate up to ~20 µm if charge information is utilized.
• Temporal Resolution:
  • Results vary by layout and pitch. The APTS (10 µm pitch) achieved 63 ps (N-gap) and 189 ps (Standard) using constant-fraction discrimination.
  • Larger pitches (e.g., H2M at 35 µm) suffer from time-walk effects, resulting in resolutions of ~28 ns.
  • Achieving the 5 ns target for future colliders will likely require time-walk corrections and is challenging for pitches >15 µm.
• Charge Collection: The N-gap layout significantly reduces charge sharing compared to the Standard layout, leading to smaller cluster sizes but potentially lower hit efficiency at high thresholds if not optimized.

Radiation Hardness

• Sensors with the N-gap layout demonstrated resilience up to $10^{14} \text{ neq cm}^{-2}$ and 3 MGy TID with negligible degradation in spatial resolution (<0.5 µm) and maintained high efficiency.
• The DPTS (N-gap) showed acceptable performance up to $10^{14} \text{ neq cm}^{-2}$, though noise increased after 100 kGy TID.
• The Standard layout is expected to be more sensitive to radiation-induced charge trapping and diffusion changes.

5. Significance and Outlook

This paper confirms the feasibility of using TPSCo 65 nm CMOS technology for future lepton collider vertex detectors, provided that specific design choices are made:

1. Layout Selection: The N-gap layout is the preferred architecture for radiation hardness and efficiency, though it requires smaller pixel pitches (<15 µm) to meet spatial resolution goals.
2. Design Trade-offs: There is a critical trade-off between spatial resolution (favored by charge sharing in Standard layouts) and radiation hardness/efficiency (favored by N-gap).
3. Future Directions: The OCTOPUS project will proceed with a systematic simulation campaign to optimize the sensor geometry (gap size, doping profiles) and front-end electronics. The goal is to finalize a demonstrator chip that simultaneously meets the strict requirements for spatial resolution (<3 µm), timing (~5 ns), power (<50 mW cm⁻²), and radiation tolerance.

The work serves as a foundational reference for the HEP community, bridging the gap between commercial CMOS imaging capabilities and the extreme demands of high-energy physics experiments.