A Novel Approach for Fault Detection and Failure Analysis of CMOS Copper Metal Stacks

This paper details the measurement and analysis methods used to identify, characterize, and resolve recurrent fault signatures in large-scale stitched CMOS copper metal stacks for the ALICE experiment's MOSS prototype, leading to a successful mitigation strategy implemented by the foundry.

The Gist

Imagine you are trying to bake a giant, perfect pizza for a massive party. The problem is, your oven (the manufacturing machine) is too small to fit the whole pizza at once. So, you decide to bake the pizza in slices, then carefully stitch them together to make one giant, seamless pie.

This is exactly what scientists at CERN (the home of the Large Hadron Collider) are doing with a new computer chip for their particle detector. They call this chip the MOSS (MOnolithic Stitched Sensor). It's a tiny silicon "pizza" that needs to be huge—so big that it has to be stitched together from smaller pieces.

Here is the story of how they found a hidden flaw in the "cheese and sauce" (the metal wiring) of this pizza and fixed it, explained simply.

1. The Big Challenge: Stitching the Silicon

The scientists needed a sensor so large it wouldn't fit on a single manufacturing template. To solve this, they used a technique called stitching. Think of it like sewing two pieces of fabric together. If you sew them poorly, the seam is weak, or the fabric bunches up.

They made a prototype (a test run) to see if this "stitching" would work without breaking the chip. They made 24 giant wafers (the raw silicon discs) and tested 20 of them.

2. The Detective Work: How to Find the "Shorts"

When they turned the power on, they expected the chips to work. Instead, they found "shorts." In electrical terms, a short is like a bridge being built where it shouldn't be—electricity takes a shortcut, bypassing the intended path, which can cause the system to overheat or fail.

To find these invisible bridges, the team used a three-step detective method:

• Step 1: The Resistance Check (The "Tug-of-War"): Before turning the power fully on, they gently tugged on the electrical wires. If the wire felt too loose (low resistance), they knew a short existed.
• Step 2: The Slow Ramp-Up (The "Warm-Up"): Instead of flipping a switch, they slowly turned up the voltage, like turning up a dimmer switch. They watched the current closely. If a short was there, the current would spike.
• Step 3: The Thermal Camera (The "Heat Vision"): This was the coolest part. They used a special camera that sees heat. When electricity took a shortcut, it created a tiny, glowing "hotspot" on the chip, just like a red spot on a thermal image of a person with a fever.

3. The Mystery: What Caused the Hotspots?

The team found hotspots on almost every chip they tested. But where were they? And why?

They had two theories:

• Theory A: The shorts happened where two specific layers of copper wiring (let's call them Layer 7 and Layer 8) crossed each other or were too close.
• Theory B: The shorts happened because of just one layer of copper being messy.

To solve the mystery, they used a FIB-SEM (Focused Ion Beam). Imagine this as a super-precise, microscopic knife that slices the chip open so they can look at the cross-section under a powerful electron microscope.

The Verdict: The microscope showed that the shorts were indeed caused by Layer 7 and Layer 8 touching each other in places they shouldn't. It was a design flaw specific to how these two new layers were stacked.

4. The "Burn-Through" Miracle

Here is the surprising twist: When they found a short, they didn't always throw the chip away.

Sometimes, when they let a little extra current flow through the short, the heat was so intense that it literally burned a hole through the tiny copper bridge causing the short. It was like using a laser to cut a knot in a rope. Once the knot was cut, the electricity flowed correctly again!

About 89% of the faulty chips could be "healed" this way. They would burn through the short, and the chip would work perfectly. However, there was a catch: sometimes the metal would expand and contract due to heat, and the bridge would reconnect, causing the short to come back.

5. The Solution: Fixing the Blueprint

The scientists didn't just fix the chips; they fixed the recipe. They told the factory (the foundry) exactly what was wrong: "Your Layer 7 and Layer 8 are too close in these specific patterns."

The factory updated their design rules to ensure those two layers never get too close again. This means future chips won't have this problem at all.

Why This Matters

This paper isn't just about fixing one chip. It's about a new way to find and fix problems in advanced technology.

• The Lesson: If you turn on a giant, complex machine too fast, you might miss small, hidden flaws.
• The Method: By checking resistance, slowly turning up the power, and using a heat camera, you can find tiny defects before they destroy the whole system.
• The Result: This method allows scientists to save money (by fixing chips instead of scrapping them) and ensures that the future particle detectors at CERN will be reliable enough to help us understand the universe.

In short: They built a giant silicon puzzle, found a few pieces that were touching where they shouldn't, used a thermal camera to spot the heat, burned the bad connections away, and then told the factory how to stop making them in the first place.

Technical Summary

1. Problem Statement

The ALICE experiment at CERN is upgrading its Inner Tracking System (ITS3) to use wafer-scale, monolithic active pixel sensors (MAPS) fabricated in 65 nm CMOS technology. These sensors require dimensions up to 97 mm × 266 mm, which exceeds the standard reticle size (~25 mm × 32 mm). Consequently, the manufacturing process relies on stitching multiple design fields together on 300 mm wafers.

To ensure high yield for these large-scale sensors, a prototype sensor called MOnolithic Stitched Sensor (MOSS) (14 mm × 259 mm) was developed. However, during the testing of 20 wafers, recurrent fault signatures (short circuits) were discovered across all samples. These faults threatened the viability of the stitching technique and the overall yield of the ITS3 upgrade. The challenge was to identify the root cause of these shorts, which were linked to a custom metal stack adaptation made by the foundry, and to develop a method to detect and analyze them before the chips were destroyed or rendered unusable.

2. Methodology

The authors developed a comprehensive, step-wise characterization and failure analysis workflow involving three main stages:

A. Impedance Measurement

• Setup: A custom setup using a channel multiplexer and a source measurement unit.
• Procedure: Impedance was measured across all 28 possible power net pair combinations for each Half Unit (HU) of the sensor.
• Criteria: A voltage ramp (0 to ±50 mV) was applied. A linear fit determined resistance. Pairs with resistance < 30 Ω were classified as "shorts."
• Goal: To identify shorted power domains without applying full operating voltage.

B. Controlled Power Ramping & Thermal Imaging

• Procedure: Power nets were ramped up individually to nominal voltage while monitoring current and using a thermal camera (640×480 pixels, 50 µm resolution).
• Observation:
  • Ohmic Turn-on: Indicated a hard short.
  • Burn-through: A transient high current followed by a sharp drop, often accompanied by a visible thermal hotspot that subsequently disappeared.
• Hotspot Localization: A semi-automated algorithm compared pre-power and during-power thermal images. It used fiducial markers for alignment, difference imaging, median blurring, and a 5×5 pixel mask scan to pinpoint the centroid of thermal anomalies with < 100 µm accuracy.

C. Correlation & Physical Validation

• Design Correlation: Extracted hotspot coordinates were overlaid with the chip layout (specifically the metal stack layers M7 and M8) to identify common design features.
• Statistical Analysis: Aggregated data from 20 wafers (1620 HUs) to identify patterns regarding wafer position and integration density.
• Physical Verification: Focused Ion Beam (FIB) cross-sectioning and Scanning Electron Microscopy (SEM) were performed on specific fault locations (both before and after burn-through) to visualize the physical defect. Energy Dispersive X-Ray Spectroscopy (EDS) confirmed the material composition.

3. Key Contributions

1. Novel Fault Detection Workflow: The paper introduces a robust, non-destructive (initially) methodology combining impedance screening, controlled power ramping, and thermal imaging. This allows for the detection of shorts that would otherwise be masked by standard power-up procedures.
2. Root Cause Identification: The study successfully identified that the faults were not random but correlated specifically with layout features involving the simultaneous presence of the top two copper metal layers (M7 and M8).
3. Hypothesis Validation: The authors formulated and validated two hypotheses:
   • Hypothesis A: Shorts occur where M7 and M8 are both present.
   • Hypothesis B: Shorts occur where only one metal layer (M7 or M8) is present.
   • Result: 94–99% of cases supported Hypothesis A, ruling out single-layer defects.
4. Mitigation Strategy: The findings provided the foundry with specific feedback to revise design rules and manufacturing processes for the M7/M8 stack, preventing recurrence in future production.

4. Key Results

• Fault Frequency: Shorts were observed on all 20 tested wafers, with significant wafer-to-wafer fluctuations (up to a factor of 10).
• Affected Nets: Shorts occurred only in combinations of Analog/Digital power and ground nets (AVDD, DVDD, AVSS, DVSS, PSUB). No shorts were found in Backbone (BB) or I/O (IO) nets.
• Location Pattern:
  • Shorts were distributed evenly between the top and bottom halves of the chip, indicating independence from integration density (line spacing).
  • They were frequently located in the gaps between pixel matrices, a region where only the M7 and M8 layers are routed.
• Burn-through Success:
  • 61.5% of HUs had no transient high current.
  • 34.2% exhibited a transient high current that resulted in a "burn-through" (the short was physically broken by the current).
  • 4.3% had persistent shorts.
  • Crucially, 89% of HUs with shorts became fully functional after the burn-through event, provided the current was sufficient to break the short but not damage the chip.
• Physical Defect: FIB-SEM analysis revealed a copper bridge connecting M7 and M8. In some cases, the thermal expansion from the burn-through created a cavity that broke the bridge. However, some burnt-through shorts were observed to reconnect due to thermal cycling, highlighting the instability of the defect.

5. Significance

• Yield Assurance for Large Sensors: The methodology is critical for the success of wafer-scale sensors like those required for the ALICE ITS3. Without this specific detection method (impedance + thermal ramping), these shorts would likely have been missed during standard testing, leading to the deployment of defective sensors or the rejection of good chips.
• Process Optimization: The study demonstrated that the custom metal stack adaptation (M7/M8) introduced a specific failure mode. The feedback loop between the experiment team and the foundry allowed for the implementation of revised design rules, ensuring the reliability of future mass production.
• General Applicability: The correlation of impedance, power-ramp behavior, thermal imaging, and layout data serves as a powerful, generalizable framework for root cause analysis in advanced CMOS devices with complex interconnect technologies.