Design and First Results of COFFEE3: A 55nm HVCMOS Pixel Sensor Prototype for High-Energy Physics Applications

This paper presents the design and preliminary test results of COFFEE3, a 55nm HVCMOS pixel sensor prototype featuring two distinct readout architectures developed to meet the stringent timing, spatial, and power requirements of future high-energy physics experiments like LHCb Upgrade II and the CEPC ITK.

The Gist

Imagine you are trying to take a photograph of a chaotic, high-speed race. But this isn't just any race; it's a race where millions of cars (particles) are zooming past your camera every second, and they are all packed incredibly tight together.

If your camera is too slow, the cars will blur into a single mess. If your camera is too big or uses too much battery, it can't fit on the race car. If your camera can't handle the heat and radiation of the track, it will break.

This is the exact problem scientists face in High-Energy Physics (like at the Large Hadron Collider). They need to track tiny particles with extreme precision, speed, and durability.

The paper you shared introduces COFFEE3, a new "camera chip" designed to solve these problems. Here is the breakdown in simple terms:

1. The Goal: The Ultimate Race Camera

The scientists are building a new sensor for future particle colliders. They need a chip that can:

• See incredibly fast: It needs to distinguish between events happening just 25 billionths of a second apart.
• Handle a crowd: It must detect up to 100 million hits per square centimeter without getting confused (like a bouncer at a club who can spot one person in a crowd of 10,000).
• Be tiny and efficient: It needs to be small enough to fit in tight spaces and use very little power so it doesn't overheat.
• Survive the radiation: The environment is like a nuclear reactor; the chip must be "radiation-hardened" so it doesn't melt or glitch.

2. The Solution: A Chip with Two Personalities

The COFFEE3 chip is special because it's like a Swiss Army Knife. It contains two different designs (architectures) on the same piece of silicon, testing two different ways to build the future.

Design A: The "Team Player" (Architecture 1)

• The Problem: In the current manufacturing process, the "sensors" (which catch the particles) and the "electronics" (which process the data) are neighbors that don't get along. They interfere with each other, like two people trying to talk in a small room.
• The Fix: This design uses only one type of electronic component (NMOS) for the sensors, keeping the "noisy" parts away from the "sensitive" parts.
• How it handles crowds: Imagine a long line of people waiting to enter a stadium. Usually, they go one by one. But if 10 people try to enter at once, the line gets stuck.
  • COFFEE3's Design A splits the line into four smaller groups.
  • It uses a two-stage pipeline: While Group 1 is being processed, Group 2 is already getting ready. This means the camera never stops to "think" between hits. It keeps the data flowing smoothly even when the crowd is huge.

Design B: The "Time Traveler" (Architecture 2)

• The Problem: The current manufacturing process is good, but scientists hope to upgrade it in the future to a version where the sensors and electronics are completely isolated (like putting a soundproof wall between neighbors).
• The Fix: This design is built for that future "perfect" factory. Because the neighbors don't interfere, the designers can put a super-precise stopwatch inside every single pixel.
• How it works:
  • Coarse Time: It counts the main clock ticks (like counting seconds on a wall clock).
  • Fine Time: This is the magic trick. Inside every pixel, there is a tiny "delay line" (a VCDL). Imagine a race track where the finish line is split into 6 tiny segments. The chip can tell exactly which segment the particle crossed, not just which second it happened.
  • The Result: It can measure time with a precision of about 4.2 nanoseconds. That's like measuring a race to the exact millimeter instead of just the meter.

3. The Results: It Works!

The team built the chip (COFFEE3) and ran some initial tests:

• The "Fake" Test: They injected electrical signals (like faking a hit) to see if the circuits reacted correctly. Pass.
• The "Laser" Test: They shot a laser at the chip to simulate a particle hitting it. The chip successfully recorded the hit, figured out exactly where it was, and sent the data out without getting lost. Pass.

4. Why Does This Matter?

Think of COFFEE3 as a prototype car for a Formula 1 team.

• They haven't raced it in the big championship yet (that's the future beam tests).
• But they have driven it around the track, checked the engine, and confirmed the brakes work.
• Now they know which design (Design A or Design B) is better for the future.

This chip is a crucial step toward building the next generation of particle detectors. These detectors will help scientists understand the fundamental building blocks of the universe, from the Big Bang to the mysterious nature of dark matter.

In a nutshell: The scientists built a tiny, super-fast, radiation-proof camera chip with two different brains inside it. They tested it, and it's ready to start the real race.

Technical Summary

1. Problem Statement

High-energy physics (HEP) experiments, specifically the LHCb Upgrade II and the Circular Electron Positron Collider (CEPC), require advanced pixel tracking systems capable of operating under extreme conditions:

• High Hit Density: The need to resolve hit densities up to 100 MHz/cm².
• Timing Precision: A time resolution of a few nanoseconds (target <5 ns) to distinguish 25 ns bunch crossings and distinguish neighboring events.
• Spatial Resolution: Fine position resolution of approximately 10 μm to reconstruct particle trajectories in magnetic fields.
• Radiation Hardness: The ability to withstand neutron fluences up to $3 \times 10^{15}$ neq/cm².
• Power Constraints: Total power consumption must remain below 200 mW/cm².

While previous sensors (e.g., ATLASPix, MightyPix) validated HVCMOS feasibility, they often used older processes (180nm/150nm). There is a critical need to leverage advanced 55nm High-Voltage CMOS (HVCMOS) processes to integrate complex analog and digital circuits in a compact area while addressing specific challenges like crosstalk in triple-well processes and achieving high-precision timing.

2. Methodology

The authors designed COFFEE3, a 55nm HVCMOS pixel sensor prototype, building upon the process validation of the previous COFFEE2 chip. The design strategy focuses on integrating two distinct readout architectures on a single chip (3×4 mm²) to test compatibility with both current and future process technologies.

• Pixel Specifications:

  • Pixel pitch: 36 μm (layout height 40 μm, scaled by 0.9 for 55nm manufacturing).
  • Expected spatial resolution: ~10 μm ($36/\sqrt{12}$).
  • Power budget: ~160 mW/cm² for the pixel array and 40 mW/cm² for peripherals.

• Architecture 1: NMOS-Only In-Pixel (Current Triple-Well Process)

  • Context: Designed for the standard 55nm triple-well process where deep-Nwell sensing diodes are prone to crosstalk with PMOS transistors.
  • Solution: Adopts an NMOS-only in-pixel circuitry (Charge Sensitive Amplifier, Comparator, 4-bit DAC) to eliminate PMOS-diode crosstalk.
  • Readout Strategy: To handle high hit densities, the architecture uses column-level readout.
    • Pixels in a column are split into groups for parallel readout to prevent pile-up.
    • Implements a two-stage pipelined signal processing unit at the End-of-Column (EOC) to record the next hit while transmitting the current one, minimizing dead time.
    • Measures Time of Arrival (TOA) and Time over Threshold (TOT) using a 25 ns system clock.

• Architecture 2: Pixel-Level Time Measurement (Future Process with P-type Buried Layer)

  • Context: Designed for a modified process featuring a p-type buried layer isolation, which eliminates crosstalk between PMOS and sensing diodes, allowing for full CMOS in-pixel designs.
  • Solution: Implements in-pixel Time-to-Digital Converter (TDC) functionality.
  • Timing Mechanism:
    • Coarse Quantization: Counts a 40 MHz system clock (25 ns period) stored in SRAM.
    • Fine Quantization: Uses a Voltage-Controlled Delay Line (VCDL) replicated in each pixel, controlled by a peripheral Delay-Locked Loop (DLL). This divides one clock cycle into six phases.
    • Power Optimization: Only the signal (DIS_OUT), not the clock, passes through the VCDL to reduce power.
    • Resolution: Achieves ~4.2 ns precision for the leading edge (TOA) and ~8.4 ns for the trailing edge (TOT).

3. Key Contributions

• Dual-Architecture Integration: Successfully integrated two different readout paradigms (column-level vs. pixel-level timing) on a single 55nm HVCMOS chip to validate both current and future process technologies.
• Advanced Process Utilization: Demonstrated the feasibility of using 55nm HVCMOS for high-density, high-speed particle tracking, moving beyond the limitations of 180nm/150nm nodes.
• Innovative Timing Circuits:
  • Developed a pipelined, group-based column readout to mitigate pile-up in high-hit-density scenarios.
  • Designed a pixel-level TDC using a VCDL/DLL architecture that achieves sub-5ns resolution without excessive power consumption.
• Crosstalk Mitigation: Validated the NMOS-only approach for triple-well processes and the p-type buried layer concept for future processes to solve diode-transistor crosstalk issues.

4. Preliminary Results

The COFFEE3 chip was fabricated in January 2025 and tested in May 2025.

• Analog Circuit Verification: Charge injection tests confirmed the correct operation of the Charge Sensitive Amplifier (CSA) and Comparator.
• Timing Circuit Verification: The DLL successfully delivered clock phase delays with each tap shifting by $\pi/3$ (60°), as expected.
• Full Readout Chain Validation:
  • Architecture 1: Laser tests and charge injection confirmed correct data formatting and address information.
  • Architecture 2: Laser tests verified TOT measurements against different thresholds, matching circuit simulations. Valid transmission packets containing correct row/column addresses were successfully received.
• Current Status: Both architectures operate as expected. Detailed characterization of TOA/TOT resolution, radiation hardness, and tracking efficiency using X-ray ($^{55}$Fe), beta-ray ($^{90}$Sr), and minimum ionizing particles (cosmic/beam) is ongoing.

5. Significance

COFFEE3 represents a critical step forward for the LHCb Upgrade II Upstream (UP) tracker and the CEPC Inner Tracker (ITK).

• It validates that 55nm HVCMOS can meet the stringent 100 MHz/cm² hit density and <5 ns timing requirements of future high-luminosity experiments.
• The dual-architecture approach provides a robust roadmap: Architecture 1 offers an immediate solution for current fabrication capabilities, while Architecture 2 paves the way for higher performance with future process modifications.
• The successful integration of in-pixel TDCs in a 55nm process demonstrates a path toward highly integrated, low-power, and high-precision tracking detectors essential for the next generation of particle physics discoveries.