Testing and Characterization of Wafer-Scale MAPS Prototypes for the ALICE ITS3 Upgrade

This paper presents the testing and characterization of two prototype wafer-scale stitched CMOS sensors, MOSS and MOST, developed for the ALICE ITS3 upgrade, demonstrating their high efficiency, radiation hardness, and the feasibility of using stitched sensors in high-energy physics experiments despite identified design-related failure modes.

The Gist

Imagine you are trying to build the ultimate, ultra-lightweight camera for a high-speed race car. This camera needs to be so thin and light that it barely adds any weight at all, yet it must be incredibly tough to withstand the heat, radiation, and chaos of the race.

This paper is about testing two "prototype cameras" (called MOSS and MOST) designed for the ALICE experiment at CERN's Large Hadron Collider. The goal is to upgrade the innermost layer of the detector that tracks particles, making it lighter and more precise.

Here is the story of how they tested these prototypes, explained simply:

1. The Big Idea: The "Stitched" Blanket

Normally, computer chips are made on small squares (wafers). But the ALICE team needed a sensor that was huge—about 26 cm long. Since standard manufacturing machines can't make chips that big in one piece, they had to get creative.

They used a technique called "stitching." Imagine sewing together several smaller patches of fabric to make one giant blanket. They took smaller sensor blocks (called RSUs) and "stitched" them together side-by-side to create one massive, continuous sensor.

• MOSS: A wide, sturdy prototype (14 mm wide).
• MOST: A narrow, dense prototype (2.5 mm wide) that also includes a stopwatch feature to time exactly when a particle hits.

2. The Power Problem: The "Electrical Short"

The biggest fear with these giant chips is a short circuit. Think of a short circuit like a leak in a dam. If you have a small dam, a leak is manageable. But if you have a massive dam (the whole chip) and a leak happens, the whole thing could flood and stop working.

• The MOSS Test: They tested 120 of these chips. They found that about 4% had "leaks" (shorts) in their power grid that couldn't be fixed. However, they discovered that some leaks could be "burned out" by applying a specific voltage, effectively sealing the hole.
• The MOST Innovation: The MOST chip had a clever safety feature called Power Gating. Imagine the chip is a city with many neighborhoods. If one neighborhood catches fire (a short circuit), MOST has automatic firewalls that can cut off power to just that neighborhood, keeping the rest of the city running. They tested this and proved the firewalls worked perfectly.

3. The "Yield" (Success Rate)

In manufacturing, "yield" is the percentage of chips that actually work.

• The Bad News: At first, many chips failed because of the "leaks" (power shorts) or because the way they read the data was too simple (like a traffic jam where two cars try to enter a highway at the exact same time).
• The Good News: Once they ignored the problems that were specific to these prototypes (and not the final design), the success rate skyrocketed.
  • MOSS: About 98% of the sensor areas worked perfectly.
  • MOST: Almost every single pixel responded correctly.

This is great news because it means they can find enough good chips to build the final detector.

4. The Stress Test: Radiation and Heat

The ALICE detector sits right in the path of high-energy particles. It's like standing in a hailstorm of invisible bullets. The team tested the chips by blasting them with radiation (simulating years of use in the collider).

• The Result: Even after being hit with a massive dose of radiation (equivalent to 4,000 years of natural background radiation in a few seconds), the MOSS sensor still worked with 99% efficiency. It didn't start "hallucinating" (creating fake hits) too often. It proved it could survive the harsh environment of the LHC.

5. The "Vision" Test: Seeing Energy

They also tested how well the chips could "see" the energy of particles. They used a special radioactive source (like a tiny flashlight that emits X-rays) to see if the chips could measure the energy accurately.

• The chips could clearly distinguish between different types of energy, much like how your eye can distinguish between a dim light and a bright one. They proved the sensors are sharp and accurate.

6. The "New Way" of Powering

The MOST chip tried a new trick for powering the sensors. Usually, you need a negative voltage to run the sensor, which is hard to distribute across a huge chip. MOST tried shifting the "ground" level instead.

• The Result: It worked! This is like finding a new way to wire a house that doesn't require running heavy, dangerous cables through every room. It simplifies the design for the future.

The Bottom Line

The paper concludes that stitching small chips together to make a giant sensor is not only possible but successful.

• They found the bugs (mostly in the power grid and the data reading system).
• They fixed the bugs in their understanding (and will fix them in the final design).
• They proved the chips can survive the radiation.

In short: The team built two giant, stitched-together prototypes. They broke a few, fixed the design, and proved that the final version will be strong enough, light enough, and smart enough to upgrade the ALICE detector for the next generation of particle physics experiments.

Technical Summary

1. Problem Statement

The ALICE experiment at the LHC is planning a major upgrade to its Inner Tracking System (ITS) during Long Shutdown 3 (LS3). The goal is to replace the innermost three layers with a novel, ultra-light, bent tracker based on Monolithic Active Pixel Sensors (MAPS).

• The Challenge: The design requires six wafer-scale sensor chips (approx. 25.9 cm long) to be bent into cylinders. These chips must be stitched together from smaller sensor units (Repeated Sensor Units or RSUs) to cover a large fraction of a 300 mm wafer.
• Key Constraints:
  • Material Budget: The tracker must be extremely light, leaving almost no material other than the silicon die in the central barrel.
  • Yield: Unlike conventional modules where defective chips can be discarded, the ITS3 design requires selecting six specific wafers where a sufficient fraction of the central area is operable. Individual chip selection is not possible.
  • Radiation Hardness: The sensors must withstand high levels of ionizing (TID) and non-ionizing (NIEL) radiation.
  • Stitching Risks: It is unproven whether stitching CMOS sensors at this scale introduces defects or yield loss at the boundaries.

2. Methodology

The authors produced and characterized two prototype ASICs fabricated in a 65 nm CMOS process to validate the feasibility of wafer-scale stitching and different design approaches:

• MOSS (MOnolithic Stitched Sensor): A 14 mm wide chip designed with lower integration density to assess yield impacts. It features a "strobed" readout with hit-latches and a power grid organized into three isolated domains per half-RSU.
• MOST (MOnolithic Stitched sensor with Timing): A 2.5 mm wide chip designed at maximum integration density. It features a "hit-driven" readout (no strobe) for Time-of-Arrival (ToA) measurements and implements granular power gating switches to isolate short circuits.

Testing Campaigns:

1. Powering Tests: Cross-impedance measurements and thermal imaging during power ramping to identify short circuits and "burn-through" events.
2. Functional Yield: Mass testing of 82 MOSS chips and 9 MOST chips involving digital/analog peripheral checks, pixel matrix readout, and performance metrics (threshold, noise, fake-hit rate).
3. Energy Calibration: Using a $^{55}$Fe source (5.9 keV and 6.5 keV photons) to measure linearity and energy resolution via Time-over-Threshold (ToT).
4. In-Beam Testing: Testing at CERN PS to measure detection efficiency and fake-hit rates under varying thresholds.
5. Radiation Hardness: Irradiation with X-rays (up to 10 kGy) and reactor neutrons (up to $10^{13}$ $1 \text{ MeV neq cm}^{-2}$) to simulate ITS3 operational conditions.
6. Biasing & Power Gating: Testing alternative biasing schemes (shifting the front-end ground) and the efficacy of power gating switches to isolate faults.

3. Key Contributions

• First HEP Application of Stitched Sensors: This work represents the first evaluation of stitched CMOS sensors in a High Energy Physics (HEP) experiment context.
• Yield Characterization: Comprehensive statistical analysis of wafer-scale prototypes, distinguishing between manufacturing defects, design flaws, and process-induced issues.
• Radiation Validation: Demonstration that wafer-scale stitched sensors can meet the stringent radiation tolerance requirements of the ALICE ITS3 upgrade.
• Design Feedback: Identification of specific failure modes (power grid shorts, readout architecture limitations) to guide the design of the final production ASIC.

4. Results

A. Yield and Defects

• Stitching Process: No defects were attributed specifically to the stitching boundaries; failures were distributed across the entire chip.
• MOSS Yield:
  • Raw Yield: ~76% per region (1/80th of a chip) considering all failures.
  • Adjusted Yield: ~98% per region when excluding failures caused by the prototype's specific readout architecture (hit-latch de-assertion issues) and power grid shorts (which are understood and mitigatable).
  • Failure Modes: Two main issues identified: power grid shorts (4.3% of half-RSUs) and readout architecture limitations.
• MOST Yield:
  • ~56% of full chips could not be powered due to global shorts.
  • However, functional testing of responsive pixels showed only 0.009% unresponsive pixels per RSU.
  • Power gating switches successfully demonstrated the ability to disconnect faulty sections, though no active faults were found requiring isolation during testing.

B. Performance Metrics

• Radiation Tolerance: MOSS operated with >99% detection efficiency and a fake-hit rate < $10^{-1}$ hits/pixel/s after irradiation to 4 kGy TID and $4 \times 10^{12}$ $1 \text{ MeV neq cm}^{-2}$ NIEL (the required levels for ITS3).
• Energy Resolution:
  • MOSS (22.5 µm pitch): 7.3 ± 0.2%.
  • MOST (18.5 µm pitch): 7.7 ± 0.2%.
  • Both showed clear Mn-K peaks and silicon fluorescence peaks, with linear charge-to-ToT response.
• Biasing: The MOST alternative biasing scheme (shifting the front-end rail) was proven effective, eliminating the need to distribute negative voltages across the chip.

5. Significance

This paper confirms the feasibility of manufacturing wafer-scale stitched MAPS for the ALICE ITS3 upgrade.

• Feasibility: The stitching process does not inherently degrade yield or performance.
• Robustness: The sensors meet the critical radiation hardness and efficiency requirements for the LHC environment.
• Design Optimization: The study identified that the primary yield losses in the prototype were due to specific design choices (readout architecture and power grid layout) rather than fundamental manufacturing limits.
• Future Outlook: With a projected yield of ~98% (excluding mitigatable issues), the production of six functional wafer-scale sensors for the final ITS3 detector is considered achievable. The data provided by MOSS and MOST is now being used to finalize the design of the production ASIC.