AI-Assisted Hardware Security Verification: A Survey and AI Accelerator Case Study

1. Problem Statement

As hardware systems, particularly AI accelerators, grow in complexity, traditional security verification methods face significant bottlenecks.

• Complexity & Threat Landscape: Modern Systems-on-Chip (SoCs) and AI accelerators contain sensitive assets (model parameters, activations, control paths) vulnerable to hardware Trojans, side-channel attacks, fault injection, and IP theft.
• Limitations of Current Workflows: Existing verification relies heavily on labor-intensive manual processes, including simulation, assertion-based verification, and model checking. These methods struggle to scale with the sheer size of modern designs and often fail to detect vulnerabilities before fabrication (pre-silicon).
• The AI/LLM Gap: While Large Language Models (LLMs) show promise in automating design tasks (RTL generation, testbench creation), their application to security verification is nascent. Key concerns include the "hallucination" of security properties, lack of grounding in formal evidence, and the difficulty of mapping high-level threats to low-level hardware implementations.

2. Methodology

The paper employs a dual-methodology approach: a comprehensive literature survey and a practical case study.

A. Survey Framework

The authors organize the state-of-the-art in AI-assisted security verification into a six-stage workflow pipeline (illustrated in Figure 1 of the paper):

1. Asset Identification: Automating the extraction of security-critical components (e.g., registers, data paths, model weights) from RTL and specifications.
2. Threat Modeling: Using LLMs to map assets to adversarial scenarios and Common Weakness Enumeration (CWE) categories.
3. Test Plan Generation: Translating threat models into executable SystemVerilog/UVM test plans and coverage targets.
4. Simulation & Formal Verification: Generating assertions, properties, and monitors to validate designs via simulation or formal proofs.
5. Countermeasure Reasoning: Analyzing vulnerabilities to propose RTL patches or architectural mitigations.
6. Grounding: Emphasizing that all AI outputs must be validated against simulation evidence and formal reasoning to ensure trust.

B. Case Study: NVDLA CSB Master

To validate the survey's concepts, the authors conducted an end-to-end automated verification workflow on the NVIDIA Deep Learning Accelerator (NVDLA), specifically the CSB (Configuration and Status Bus) Master module.

• Setup: An "agentic" workflow was used where LLMs performed asset identification, threat modeling, and test generation without human intervention for the initial steps.
• Execution:
  • Asset ID: The LLM identified CSB handshake signals, payload fields, and address decode logic as critical assets.
  • Threat Modeling: The LLM mapped the design to CWE-1220 (Insufficient Granularity of Access Control), noting that core_req_prdy is permanently asserted, allowing any requester to access downstream paths without privilege checks.
  • Test Generation: The LLM generated SystemVerilog tasks to perform directed tests, including unprivileged writes to DMA-facing targets and full address scans.
  • Simulation: The generated tests were run against the RTL. Monitors tracked handshake acceptance and forwarding behavior.
  • Countermeasures: Based on simulation results, the LLM proposed specific RTL fixes (e.g., gating core_req_prdy on authorization checks).

3. Key Contributions

1. Comprehensive Taxonomy: The paper provides the first structured survey organizing AI/LLM applications across the entire hardware security verification lifecycle, from asset discovery to countermeasure reasoning.
2. Identification of Critical Challenges: It highlights that while LLMs can accelerate workflow orchestration, they suffer from hallucinations and lack of "grounding." The authors argue that AI outputs must be strictly validated by simulation and formal methods.
3. Practical Case Study (NVDLA): The paper demonstrates a working, automated pipeline on a real-world, open-source AI accelerator. It proves that LLMs can successfully:
   • Identify security-relevant assets in complex IP.
   • Map design flaws to standard CWEs.
   • Generate functional testbenches that successfully expose vulnerabilities.
   • Propose actionable RTL countermeasures.
4. Research Questions (RQs): The paper defines three critical open questions for the community:
   • How to automate the end-to-end workflow for accelerators?
   • How to ground AI artifacts in simulation/formal methods to reduce hallucinations?
   • What benchmarks and abstractions are needed for scalable, trustworthy evaluation?

4. Results

• Vulnerability Discovery: In the NVDLA case study, the automated workflow successfully identified a privilege escalation vulnerability.
  • Finding: The CSB master accepted and forwarded 30 out of 31 exercised transactions (29 writes, 1 read) to decoded sub-units without any local privilege check.
  • Specifics: The core_req_prdy signal was permanently high (line 468), and no source-ID or privilege metadata was checked before forwarding requests.
• Test Effectiveness: The LLM-generated test plan successfully covered 17 mapped targets and 1 unmapped target. The simulation confirmed that unauthorized requests could reach sensitive DMA interfaces.
• Countermeasure Generation: The system correctly identified that the fix must occur at the request-admission boundary (the CSB master) rather than patching individual downstream targets, proposing specific design changes (R1-R3 in Table IV).

5. Significance

• Paradigm Shift: The paper argues for a shift from purely manual, expert-driven security verification to AI-augmented, agentic workflows. This is crucial for keeping pace with the complexity of modern AI accelerators.
• Trustworthy Automation: By emphasizing the need for "evidence-backed claims" (simulation results, formal proofs), the paper provides a roadmap for integrating LLMs into safety-critical hardware design without compromising security assurance.
• Scalability: The case study demonstrates that automated workflows can rapidly analyze complex IP blocks (like NVDLA) that would take human engineers significant time to audit manually.
• Foundation for Future Research: The identified research questions and the proposed pipeline serve as a blueprint for developing standardized benchmarks (like HardsecBench mentioned in references) and tools for the next generation of hardware security verification.

In conclusion, this paper establishes that while AI/LLMs are not yet a "silver bullet" for hardware security, they are powerful force multipliers when integrated into a rigorous, simulation-grounded verification pipeline. The NVDLA case study serves as a proof-of-concept that automated agents can effectively detect, analyze, and propose fixes for real-world hardware vulnerabilities.