Behavioral-Level Simulation of Digital Readout for COFFEE at LHCb Upstream Pixel Tracker

This paper presents behavioral-level simulations of the digital readout for the COFFEE HVCMOS pixel sensor, demonstrating that its column-drain mechanism achieves nearly 100% efficiency at LHCb Upgrade II hit rates and providing design guidance for the COFFEE3 and CHiR chips.

The Gist

Imagine you are trying to take a photo of a massive, chaotic mosh pit at a rock concert. The crowd is so dense and moving so fast that people are bumping into each other every millisecond. Now, imagine your camera isn't just one lens, but a grid of 46,000 tiny, super-fast eyes (pixels) that need to record every single bump instantly.

This is exactly the challenge facing the LHCb experiment at CERN's Large Hadron Collider. They are upgrading their "Upstream Pixel Tracker" (a high-tech camera for subatomic particles) to handle the most intense particle collisions ever created. To make sure their new camera, called COFFEE, doesn't get overwhelmed and miss any data, the team ran a massive computer simulation.

Here is a breakdown of what they found, using some everyday analogies:

1. The Problem: A Traffic Jam in a Tiny City

The new detector will be placed very close to the particle beam. It's like standing right next to a highway during rush hour. The particles (cars) are hitting the sensor (the road) at a rate of 322.5 million times per second on the busiest chips.

If the sensor is too slow to process a "hit" (a car passing by) before the next one arrives, it misses the data. This is called "efficiency loss."

2. The Solution: The "Token Passing" Traffic Light

The COFFEE sensor uses a clever system called Column-Drain Readout.

• The Analogy: Imagine a long line of people (pixels) waiting to hand a note to a manager (the readout controller). To keep things orderly, they pass a "token" (like a talking stick) down the line. Only the person holding the token can speak.
• The Finding: The simulation showed that if the manager takes too long to listen to each person (more than 100 nanoseconds, which is a billionth of a second), the line gets backed up. People start dropping their notes because the line is too long.
• The Result: As long as the manager listens quickly (under 100ns), the system works at nearly 100% efficiency. If they are slower, the system starts missing data, and the "misses" aren't even spread out evenly—they cluster in the busiest areas, which would mess up the physics data.

3. The Bursty Crowd: Handling the "Long Tail"

Sometimes, the crowd doesn't just flow steadily; they surge. In a split second, a huge group might hit the sensor all at once.

• The Analogy: Imagine a bank teller. Most of the time, only one or two people are in line. But occasionally, a tour bus arrives, and 50 people jump out at once. If the bank only has a waiting room for 10 people, 40 will leave without being served.
• The Challenge: The simulation showed that while most "bursts" are small, there are rare, massive surges (up to 61 hits at once) that require a huge waiting room (memory buffer).
• The Fix: The team designed a Multi-Bank Circular Buffer. Think of this as a giant, rotating carousel of storage bins.
  • It has many bins (banks) that rotate.
  • When a massive surge hits, the system spins the carousel fast enough to catch all the data.
  • The Catch: To catch the rare massive surges, you need a lot of empty bins sitting there most of the time. It's like having a stadium-sized parking lot that is 99% empty, just in case a parade comes through. The simulation confirmed they have enough space in the 55nm chip to build this "stadium," even if it feels wasteful.

4. The Exit: Getting Data Out the Door

Once the data is caught, it has to be sent out of the chip to a computer.

• The Analogy: Imagine the data is water, and the chip has six fire hoses (output links) to spray it out.
• The Finding: The simulation showed that with their new "Compact" data format (compressing the notes to make them smaller), the six hoses are working at nearly 100% capacity. They are spraying water as fast as physically possible without bursting. This means the system is perfectly sized to handle the heaviest traffic jams without clogging.

The Bottom Line

The team built a digital "wind tunnel" to test their new camera design before they actually built it.

1. Speed is King: The sensor must read data incredibly fast (under 100ns) to avoid missing particles.
2. Memory is Heavy: They need a massive, somewhat wasteful memory buffer to catch rare, huge surges of data.
3. It Works: The design is solid. The "COFFEE3" chip (built in 2025) will use the fast reading method, and the "CHiR" chip (built in 2026) will use the massive memory buffer to handle the data surges.

In short, they successfully proved that their new camera won't get a "blurred" photo of the universe's most energetic collisions, even when the crowd gets crazy.

Technical Summary

1. Problem Statement

The LHCb Upgrade II will operate with proton-proton collisions at 14 TeV and a luminosity of $1.0 \times 10^{34} \text{ cm}^{-2}\text{s}^{-1}$. The Upstream Pixel (UP) tracker, located merely 4 cm from the beam pipe, faces extreme particle hit rates, reaching up to 322.5 MHz per chip.

• Challenge 1 (Efficiency): The high hit density causes data pileup. If the readout mechanism cannot clear data fast enough, new hits are ignored, leading to significant detection efficiency loss.
• Challenge 2 (Bandwidth & Memory): To manage output link bandwidth, the system uses a "Bunch Crossing (BX) grouping" data format. This requires handling rare, high-intensity bursts of hits within a single BXID, necessitating large memory resources to prevent data loss.
• Challenge 3 (Non-uniformity): Hit rates are not uniform across the chip; they fluctuate significantly, creating "bursty" traffic patterns that average density models fail to capture accurately.

2. Methodology

The authors performed a behavioral-level simulation using SystemC to model the digital readout circuitry of the COFFEE series HVCMOS pixel sensors (55 nm process).

• Input Data: Instead of using averaged hit densities, the simulation fed 50,000 Monte Carlo (MC) minimum-bias proton-proton collision events into the testbench. This captured realistic fluctuations, non-uniform distributions, and bursty traffic.
• Simulation Scope:
  • Pixel Array: Modeled the column-drain readout mechanism (token passing scheme) used in COFFEE3.
  • Peripheral Readout: Modeled the architecture adapted for BXID-sharing data formats, including FIFOs, circular buffers, and serialization logic.
  • Parameters: Varied the "READ signal width" (single readout cycle duration) and analyzed Time Over Threshold (TOT) distributions (Landau distribution, 200–1500 ns).

3. Key Contributions

• Realistic Traffic Modeling: Demonstrated the necessity of using MC event-based simulations rather than averaged values to accurately predict efficiency loss and memory requirements due to bursty hit patterns.
• Readout Cycle Optimization: Established a critical threshold for the single readout cycle time to maintain near-100% efficiency in high-luminosity environments.
• BXID-Sharing Architecture Design: Proposed and evaluated a peripheral readout architecture featuring a globally shared multi-bank circular buffer to handle the specific data format requirements of the UP tracker.
• Resource Quantification: Provided precise metrics for memory depth (FIFO and buffer sizes) and bandwidth utilization required for the most extreme hit-rate scenarios.

4. Key Results

A. Column-Drain Readout Efficiency

• Critical Threshold: The simulation revealed that the READ signal width must be $\le$ 100 ns to maintain nearly 100% detection efficiency.
• Consequences of Delay: If the cycle exceeds 100 ns, efficiency drops significantly. Furthermore, due to non-uniform hit distributions, efficiency becomes non-uniform across different double columns, potentially introducing systematic biases in reconstructed physics quantities.
• Implementation: The 100 ns constraint was adopted for COFFEE3 (fabricated in 2025).

B. Peripheral Readout & Memory Requirements

• Latency Distribution: The latency from hit to data packet arrival at the circular buffer is mostly within 80 clock cycles (driven by TOT), but a "long tail" extends up to 215 clock cycles due to pixel queuing.
• Memory Trade-off: Truncating the long tail to save memory results in efficiency loss. The simulation determined that a FIFO depth of approximately 23 is required for the frontend of the multi-bank circular buffer to handle the worst-case bursts without loss.
• Architecture: The design utilizes a multi-bank circular buffer (16-bit width) where banks are read cyclically at 40 MHz. The on-chip TOA correction eliminates the need to transmit TOT bits off-chip, saving bandwidth.

C. Bandwidth Utilization

• Configuration: The backend uses six 8-bit to 1-bit serializers.
• Performance:
  • Chip 1 (274.9 MHz): With six 1.28 Gbps links, bandwidth utilization ranges from 99.5% down to 39.3% (due to prioritization). Max asynchronous FIFO occupancy is 4.
  • Chip 2 (322.5 MHz - Hottest): Utilization ranges from 99.8% down to 67.3%. Max FIFO occupancy is 6.
• Conclusion: The proposed link configuration is sufficient to handle the data volume of the highest hit-density regions.

5. Significance and Future Work

• Design Guidance: The simulation results directly guided the design of COFFEE3 (100 ns readout cycle) and the CHiR chip (taped out early 2026), which implements the BXID-sharing peripheral architecture.
• Feasibility: The study confirms that the advanced 55 nm process provides sufficient area for the required memory resources, though optimization is needed as most memory remains idle during non-burst periods.
• Future Directions:
  • Implementation of intelligent scheduling algorithms to optimize the idle memory usage.
  • Conducting a global simulation that includes back-pressure mechanisms (currently, the simulation assumed ideal, back-pressure-free backend conditions).

In summary, this paper validates the digital readout architecture for the LHCb UP tracker, proving that strict timing constraints (100 ns) and specific memory buffering strategies are essential to handle the unprecedented hit rates of the LHCb Upgrade II.