Resist-free shadow deposition using silicon trenches for Josephson junctions in superconducting qubits

This paper presents a resist-free Josephson junction fabrication method using etched silicon trenches that eliminates chemical contamination, achieves median energy relaxation times up to 184 microseconds, and offers a CMOS-compatible, scalable alternative to traditional polymer-masked processes for superconducting qubits.

The Gist

Imagine you are trying to build a super-precise, microscopic clock that runs on electricity. This clock is a superconducting qubit, the heart of a quantum computer. For this clock to work, it needs a very specific, tiny switch called a Josephson Junction (JJ). Think of this junction as the "heartbeat" of the quantum computer; if it's dirty or imperfect, the clock loses time, and the computer makes mistakes.

For the last 25 years, scientists have built these heartbeats using a method that is a bit like painting a stencil.

1. They put a layer of sticky plastic (called "resist") on a silicon chip.
2. They cut a shape into the plastic with a laser.
3. They spray metal (aluminum) onto the chip. The metal lands on the exposed silicon but gets blocked by the plastic.
4. They wash away the plastic, leaving the metal behind.

The Problem:
The "plastic stencil" is the villain in this story. When you use plastic, it leaves behind invisible chemical residue (like grease on a pan) and traps dirt. This contamination ruins the purity of the metal switch. It's like trying to bake a perfect cake but using a mixing bowl that still has old, sticky batter stuck to the sides. No matter how clean you try to be, the cake tastes a little "off." This limits how fast and accurate the quantum computer can be.

The New Solution: The "Silicon Canyon"
The researchers at Cornell University came up with a brilliant, cleaner idea. Instead of using a plastic stencil, they carved a tiny trench (a deep, narrow canyon) directly into the silicon chip itself.

Here is how their new method works, using a creative analogy:

• The Setup: Imagine a flat road (the silicon chip). The researchers dig a deep, narrow trench in the middle of the road.
• The Shadow: They stand on a hill to the left and spray paint (aluminum) onto the road. Because of the trench, the paint hits the left side of the road and the left wall of the trench, but the right wall of the trench casts a shadow. The paint cannot reach the bottom of the right side.
• The Switch: Then, they move to a hill on the right and spray paint again. This time, the paint hits the right side and the right wall, but the left wall casts a shadow.
• The Magic Overlap: In the very middle of the trench, where the shadows from both sides meet, there is a tiny gap where no paint was sprayed from either side. But wait! Because the trench is narrow, the paint sprayed from the left side climbs up the left wall and drips over the top, and the paint from the right side does the same. They meet in the middle, creating a perfect, clean bridge.

Why is this better?

1. No Plastic, No Gunk: Since they didn't use any plastic stencils, there is no chemical residue left behind. The metal sits directly on the clean silicon. It's like baking that cake in a brand-new, sterile bowl.
2. CMOS Compatible: This method uses the same tools and techniques that the entire semiconductor industry (like Intel and TSMC) already uses to make computer chips. This means it's easy to scale up and mass-produce.
3. Better Performance: The qubits they built with this "trench" method are incredibly stable. They measured a "relaxation time" (how long the quantum state lasts) of 184 microseconds. That's a huge number in the quantum world.
4. Stability: The researchers watched these qubits for 36 hours. Instead of the performance jumping around wildly (like a shaky hand), it stayed very steady, following a smooth, predictable pattern.

The Bottom Line
This paper introduces a new way to build the most critical part of a quantum computer by ditching the messy, dirty plastic stencils of the past. By carving tiny canyons into silicon and using shadows to create the switch, they created a cleaner, more reliable, and scalable path forward. It's a simple but powerful shift: stop using plastic masks and start using the silicon itself to do the work. This opens the door to building larger, more powerful quantum computers that don't get confused by their own dirt.

Technical Summary

1. Problem Statement

Superconducting qubits, particularly transmons, have made significant strides in coherence times through improvements in base layer fabrication and materials. However, the fabrication of the Josephson Junction (JJ)—the non-linear inductive element essential for qubit operation—has remained largely unchanged for 25 years.

• Current Limitation: The standard method relies on a polymer resist liftoff process (Dolan bridge). This involves double-angle evaporation through a resist mask.
• Consequences:
  • Chemical Contamination: The polymer mask introduces carbon and oxygen residues at the metal-substrate interface, creating lossy two-level systems (TLS).
  • Process Constraints: The presence of resist limits surface preparation options (e.g., aggressive cleaning), restricts the choice of junction materials, and hinders scalability.
  • Fluctuations: Qubit coherence times ($T_1$) often exhibit non-Gaussian fluctuations over time, limiting the reliability of large-scale quantum error correction.
• Goal: Develop a fabrication method that eliminates polymer resist, minimizes interface contamination, maintains the simplicity of shadow evaporation, and is compatible with standard CMOS processes.

2. Methodology

The authors propose a resist-free, trench-based shadow evaporation technique using etched silicon substrates.

• Substrate Preparation (CMOS Compatible):

  1. Oxidation: A high-resistivity Si(100) wafer is thermally oxidized to grow a SiO$_2$ hard mask.
  2. Patterning: Electron-beam lithography defines the trench pattern on the SiO$_2$.
  3. Etching: The SiO$_2$ is dry-etched, followed by dry-etching of the Silicon substrate using an HBr/Ar process to create deep, smooth-walled trenches.
  4. Mask Removal: The SiO$_2$ hard mask is stripped using hydrofluoric acid (HF).
  5. Cleaning: The chip is soaked in buffered oxide etch (BOE) immediately before deposition to remove native oxides and any residues, ensuring a pristine surface.

• Junction Deposition:

  • Shadow Evaporation: The chip is loaded into an electron-beam evaporator.
  • Bottom Electrode: Aluminum (Al) is deposited at a $+49^\circ$ angle.
  • Oxidation: The bottom electrode is oxidized in 1 Torr of O$_2$ for 5 minutes to form the tunnel barrier (AlO$_x$).
  • Top Electrode: A second Al layer is deposited at a $-49^\circ$ angle.
  • Mechanism: The trench sidewalls act as a shadow mask. The overlap region (the junction) forms only where the trench is wide enough for the two angled beams to intersect. Narrower parts of the trench result in single-layer electrodes.

• Qubit Definition:

  • The entire qubit circuit (capacitors, resonators) is defined using a single wet etch step on the Al film, followed by resist stripping, oxygen plasma descum, and a gentle vapor HF cleaning. No additional metal deposition is required.

3. Key Contributions

• Novel Fabrication Scheme: Introduction of a fully inorganic, resist-free shadow evaporation process using etched silicon trenches.
• CMOS Compatibility: The process utilizes standard semiconductor etching and cleaning techniques, making it scalable and integrable with existing foundry technologies (up to 200 mm wafers).
• Material Agnosticism: By removing the polymer mask, the process allows for a wider range of materials and surface treatments that were previously incompatible with resist liftoff.
• Interface Purity: The method enables full in-situ surface preparation, theoretically eliminating the "halo" of hydrocarbon contamination common in resist-based processes.

4. Results

• Junction Characterization:

  • Microscopy: Scanning Transmission Electron Microscopy (STEM) and Electron Energy Loss Spectroscopy (EELS) confirmed no detectable carbon or oxygen at the Si/Al interface. The oxide barrier thickness was measured at 1.6–1.9 nm.
  • Electrical Performance: Fabricated Al-AlO$_x$-Al JJs showed critical current densities ($J_C$) around 72 A/cm$^2$, consistent with transmon requirements.

• Qubit Performance:

  • Coherence Times: The team fabricated transmon qubits with a median energy relaxation time ($T_1$) of 184 µs and a maximum quality factor ($Q_1$) of 3.26 million.
  • Gap Dependence: Performance was found to be dependent on the capacitor gap size, indicating that surface participation losses dominate for smaller gaps.
  • Fluctuation Analysis:
    • $T_1$ fluctuations were measured over a 36-hour period.
    • The fluctuations followed a narrow, normally distributed (Gaussian) pattern with a mean of 140.8 µs.
    • Stability: The robust coefficient of variation (RCV) was < 0.2, significantly lower than comparable resist-based qubits (typically 0.2–0.3+).
    • Noise Spectroscopy: Power Spectral Density (PSD) and Allan deviation analyses showed no evidence of strong, single two-level system (TLS) switching events, suggesting the noise floor is dominated by white noise or weakly coupled TLSs rather than discrete, strong fluctuators.

5. Significance

• Scalability and Reproducibility: The resist-free approach removes a major source of chemical contamination and process variability, leading to more reproducible qubit performance. The narrow distribution of $T_1$ fluctuations suggests this method could reduce the need for frequent qubit recalibration in large-scale processors.
• Process Window Expansion: By eliminating the polymer mask, the method opens the door to exploring new electrode materials, tunnel barriers, and aggressive substrate cleaning/annealing techniques that were previously impossible with resist-based liftoff.
• Path to State-of-the-Art: While the current $T_1$ (184 µs) is not yet the absolute state-of-the-art (which can exceed milliseconds), the performance is comparable to earlier generations of resist-based qubits and significantly better than other novel junction schemes. The authors argue that integrating this clean fabrication method with advanced base-layer materials (e.g., tantalum) could rapidly push coherence times to new limits.
• Industrial Relevance: The use of standard silicon etching and CMOS-compatible steps makes this approach highly attractive for transitioning superconducting qubit fabrication from research labs to industrial foundries.

In conclusion, this work demonstrates that silicon trench shadow evaporation is a viable, high-performance alternative to traditional resist-based JJ fabrication, offering a cleaner interface, superior stability, and a clear pathway for scalable quantum computing hardware.