Scalable 3D silicon nitride photonic interposer for high-density optical interconnects

This paper presents a scalable 3D silicon nitride photonic interposer prototype that utilizes a globally optimized routing scheme to achieve a fully connected 12-node network with a 69.7% reduction in waveguide crossings and a 45.8% reduction in average loss compared to all-planar designs, offering a promising solution for high-density, energy-efficient optical interconnects in next-generation computing systems.

The Gist

Imagine you are trying to organize a massive party in a single-story house where 12 guests (the "nodes") all need to talk to every single other guest at the same time.

In the old way of doing things (the all-planar approach), everyone has to stay on the same floor. To let Guest A talk to Guest B, you have to lay a long string (a wire or fiber) across the room. But because everyone needs to talk to everyone, these strings end up crisscrossing over and over each other.

The Problem: The "Tangled Yarn" Effect
In a 2D house, if you have 12 guests, you end up with 495 places where these strings have to jump over or under each other just to avoid a knot. Every time a string crosses another, it loses a little bit of signal strength (like a whisper getting quieter as it passes through a crowd). If you try to add more guests, the number of tangles explodes, making the system slow, hot, and inefficient. It's like trying to untangle a ball of yarn that keeps getting bigger.

The Solution: Building a Second Floor
The researchers at the University of Hong Kong asked a simple question: "What if we built a second floor?"

They created a 3D Silicon Nitride Photonic Interposer. Think of this as a tiny, high-tech two-story building for light signals.

• Layer 0 (The Ground Floor): Some strings stay on the bottom.
• Layer 1 (The Second Floor): Other strings go up a ramp (called an "interlayer taper") to the top floor.

By splitting the traffic between two floors, they drastically reduced the number of places where strings have to cross. Instead of 495 tangles, they only needed 150. They even managed to beat the theoretical "best possible" limit for a single-floor house!

The Magic Ingredients

1. The Material (Silicon Nitride): They used a special material called Silicon Nitride. Imagine it as a super-smooth, glass-like highway for light. It's transparent, doesn't get hot easily, and is compatible with the same factories that make computer chips.
2. The Architect (The Algorithm): They didn't just guess where to put the strings. They used a smart computer program (a "Global Optimization Algorithm") that acted like a super-architect. It simulated millions of different floor plans, looking for the one that caused the least amount of traffic jams and signal loss.
3. The Elevators (Interlayer Tapers): To move light from the bottom floor to the top without losing energy, they built special "ramps" that gently guide the light up, like a smooth slide rather than a steep drop.

The Results: A Faster, Cooler Party
When they tested their prototype:

• Less Tangled: They reduced the number of crossings by 70%.
• Clearer Signal: Because there were fewer crossings, the average signal loss dropped by 45.8%. The whispers stayed loud and clear.
• Scalable: This design isn't just for 12 guests. Because the two floors are symmetrical (like a mirror image), you can easily copy the pattern to add 24, 50, or even 100 guests without the system collapsing under its own weight.

Why Does This Matter?
Right now, our computers and AI systems are hitting a "wall." Moving data between chips using copper wires is becoming too slow and uses too much electricity. This new 3D light-based system is like upgrading from a crowded, one-lane dirt road to a multi-lane, high-speed maglev train.

It allows future supercomputers and AI data centers to move massive amounts of data quickly, efficiently, and without overheating, paving the way for the next generation of technology.

In a Nutshell:
They took a messy, tangled 2D problem and solved it by building a 3D structure. By using smart math and a special light-friendly material, they created a "highway system" for computer chips that is much faster, cleaner, and ready to handle the massive data demands of the future.

Technical Summary

1. Problem Statement

Modern high-performance computing (HPC) and artificial intelligence (AI) workloads face a critical bottleneck in data movement between compute units. While Co-packaged Optics (CPO) addresses long electrical paths, it introduces new challenges:

• Fiber Density Constraints: As bandwidth demands grow, the sheer number of required fibers creates physical and cost constraints on chip shorelines.
• All-Planar Routing Limitations: Traditional 2D (planar) photonic interposers suffer from a rapid escalation of unavoidable intralayer waveguide crossings.
  • For a fully connected network of $k$ nodes, the total number of crossings scales as $\propto k^4$.
  • Each crossing introduces significant propagation loss and crosstalk, severely constraining the link loss budget.
  • Existing material platforms (polymers, glass) have trade-offs: polymers have higher loss, while glass waveguides require large bending radii, limiting routing density.

2. Methodology

The authors propose and demonstrate a 3D dual-layer Silicon Nitride (SiN) photonic interposer to overcome topological limits.

• Material Platform:

  • Utilizes Silicon Nitride (SiN) for its wide transparency, low thermo-optic coefficient, and CMOS compatibility.
  • Structure: A dual-layer stack consisting of two 400 nm SiN layers separated by a 1 µm SiO₂ spacer, capped with a 1.5 µm SiO₂ cladding.
  • Fabrication: Uses Plasma Enhanced Chemical Vapor Deposition (PECVD). Key process steps include Chemical Mechanical Planarization (CMP) to ensure layer flatness, Stress-Release Patterns (SRPs), and high-temperature annealing to minimize film stress and propagation loss.

• Routing Architecture & Optimization:

  • 3D Strategy: Instead of confining all waveguides to a single plane, the design utilizes two vertical layers. Waveguides cross between layers using interlayer tapers (inverse tapers for adiabatic mode transfer), converting high-loss intralayer crossings into low-loss interlayer crossings.
  • Algorithm: A Generalized Simulated Annealing (GSA) algorithm is employed to optimize the routing.
    • Objective: Minimize the average on-chip interconnect loss (ICL).
    • State Space: A layer vector assigning each Optical I/O (OIO) link to Layer 0 or Layer 1.
    • Result: The algorithm generates a routing scheme with inherent rotational symmetry (Layer 1 is a 90° rotation of Layer 0), facilitating scalability.

• Prototype Design:

  • A 12-node fully interconnected network ($k=12$) is implemented on a compact 7.4 mm × 7.4 mm die.
  • Fiber-to-chip coupling is achieved via edge couplers on the bottom layer (Layer 0).

3. Key Contributions

1. Topological Breakthrough: The first demonstration of a 3D SiN interposer that breaks the theoretical lower bound of crossings for all-planar routing.
2. Algorithmic Optimization: Development of a GSA-based global optimization strategy specifically tailored for 3D photonic routing to minimize loss.
3. Scalable Architecture: A design that is inherently symmetric and scalable to higher node counts, additional routing layers, and different wavelengths without fundamental redesign.
4. Fabrication Process: A robust dual-layer PECVD SiN process flow incorporating stress management and planarization techniques suitable for high-density integration.

4. Experimental Results

The fabricated prototype was characterized to validate the 3D routing benefits against a theoretical all-planar baseline.

• Crossing Reduction:

  • All-Planar Baseline: Theoretical minimum of 495 intralayer crossings for a 12-node network.
  • 3D Prototype: Achieved only 150 intralayer crossings.
  • Improvement: A 69.7% reduction in crossings, successfully dropping below the theoretical lower bound of 153 for planar interconnects.

• Loss Performance:

  • Component Losses:
    • Intralayer crossing (Layer 0): 0.123 dB; (Layer 1): 0.169 dB.
    • Interlayer crossing: ~0.001 dB (negligible).
    • Interlayer taper transition: 0.360 dB.
    • Waveguide propagation: 0.038 dB/cm.
  • Average Link Loss (ICL):
    • Measured 3D Prototype: Mean $\mu = 2.69$ dB.
    • Predicted All-Planar Baseline: Mean $\mu = 4.96$ dB.
    • Improvement: A 45.8% reduction in average loss per waveguide compared to the planar baseline.
  • Uniformity: The standard deviation of loss ($\sigma = 2.33$ dB) was comparable to the planar baseline, though slightly higher than the idealized 3D prediction ($\sigma = 1.03$ dB).

• Discrepancy Analysis: The measured loss was slightly higher than the idealized 3D prediction (1.92 dB) due to fabrication non-uniformities, specifically higher coupling losses on the east-side edge couplers (ports 3–5) and minor thickness deviations in the waveguide layers.

5. Significance

• Enabling Next-Gen HPC: This work provides a scalable solution to the "interconnect bottleneck" in AI and HPC clusters, allowing for denser node integration without the exponential loss penalty of 2D routing.
• Loss Budget Management: By converting high-loss crossings to low-loss interlayer transitions, the 3D architecture significantly relaxes the link loss budget, enabling longer reach or higher data rates.
• Future Scalability: The demonstrated symmetry and optimization framework suggest that as node counts increase, the 3D approach will yield even more substantial gains over planar designs (reducing crossings from $\propto k^4$ to a much lower polynomial order).
• Platform Versatility: The SiN platform is compatible with standard CMOS processes, making this a viable path for mass production of high-density optical interposers for future data centers.