Algorithm and Hardware Co-Design for Efficient Complex-Valued Uncertainty Estimation

1. Problem Statement

Complex-Valued Neural Networks (CVNNs) offer significant advantages over Real-Valued Neural Networks (RVNNs) for tasks involving complex data (e.g., radar imaging, MRI, weather forecasting). However, existing CVNNs lack the ability to quantify predictive uncertainty, which is critical for reliability in safety-critical applications.

While Bayesian Neural Networks (BayesNNs) using Monte Carlo Dropout exist for real domains, extending them to complex domains presents three major challenges:

1. Theoretical Gap: It was unproven whether dropout-based Bayesian approximations are mathematically valid for complex-valued weights.
2. Exponential Design Space: Complex values have real and imaginary components. This creates a "dual-part" nature, allowing for mixed configurations (dropout on real only, imaginary only, or both). This expands the design space exponentially ($3^N$ for $N$ layers) compared to real domains, making manual architecture design inefficient and suboptimal.
3. Hardware Overhead: Complex arithmetic requires at least four real-valued operations per complex operation, doubling memory footprint and quadrupling computational complexity. Deploying Bayesian CVNNs (which require multiple forward passes) on hardware is prohibitively expensive without specialized optimization.

2. Methodology

The authors propose a comprehensive Algorithm-Hardware Co-Design framework consisting of four main stages:

A. Mathematical Foundation (BayesCVNNs)

• Extension of Dropout: The paper mathematically proves that applying Dropout to Complex-Valued Neural Networks is a valid Bayesian approximation.
• Variational Inference: By treating complex weights ($W = W_{real} + jW_{imag}$) as stochastic variables, the authors derive variational objectives. They demonstrate that dropout can be applied to the real part, the imaginary part, or both, allowing the model to capture uncertainty even if dropout is applied to only one component.

B. Automated Evolutionary Search

To navigate the exponentially larger design space ($3^N$ configurations), the authors developed an automated search approach:

• Design Space: Allows for Layer-Mixing (different layers having different dropout strategies) and Part-Mixing (real vs. imaginary dropout).
• Evolutionary Algorithm: Uses a population-based search (mutation and crossover) to find optimal configurations.
• Multi-Objective Optimization: The search optimizes for algorithmic metrics (Accuracy, Expected Calibration Error - ECE) while strictly adhering to hardware constraints (e.g., maximum number of dropout layers).

C. Hardware Mapping & Accelerator Generation

A framework generates customized FPGA accelerators using High-Level Synthesis (HLS):

• Building Blocks: A set of modular hardware blocks is created for complex layers (Conv, FC, Pooling, Activation) and the novel Complex Dropout layer.
• Mapping Schemes: Two strategies are proposed to trade off between latency and resources:
  • Latency-Opt: Deploys four parallel engines for complex multiplication (Real-Real, Real-Imag, Imag-Real, Imag-Imag) to minimize latency at the cost of higher resource usage.
  • Resource-Opt: Reuses a single real engine and a single imaginary engine sequentially to process data, saving resources but increasing latency.
• Dynamic Switching: The hardware includes switches to support "Part-Mixing" configurations, allowing the accelerator to dynamically route data to the correct dropout engine based on the specific layer configuration.

3. Key Contributions

1. First Dropout-Based BayesCVNN: The paper introduces the first Bayesian Complex-Valued Neural Network architecture that enables uncertainty quantification, with a mathematical proof validating the approach.
2. Automated Search for Mixed Configurations: A novel evolutionary search algorithm that explores a significantly larger design space ($3^N$) than real-domain BayesNNs, identifying optimal "layer-mixing" and "part-mixing" configurations that outperform manual designs.
3. Algorithm-Hardware Co-Design Framework: A complete pipeline from model search to FPGA bitstream generation. It includes specialized hardware building blocks and flexible mapping schemes (Latency-Opt vs. Resource-Opt) tailored for complex-valued Bayesian inference.
4. Quantified Overheads: The study provides a detailed analysis of the hardware costs associated with converting RVNNs to CVNNs and CVNNs to BayesCVNNs, demonstrating that the overhead is manageable and predictable.

4. Experimental Results

The framework was evaluated on datasets including MNIST (complex version), Radar-based Human Activity Recognition (HAR), and Synthetic Aperture Radar (SAR) data.

• Algorithmic Performance:

  • The automated search consistently found configurations superior to manually designed "uniform" models (where dropout is applied identically to all parts).
  • Searched configurations achieved 0.5% to 2% higher accuracy and significantly lower Expected Calibration Error (ECE), indicating better uncertainty estimation.
  • The search successfully identified Pareto-optimal designs that balance accuracy and hardware cost (number of dropout layers).

• Hardware Performance (FPGA vs. GPU):

  • Speedup: The FPGA accelerators achieved 4.5× to 13× speedups compared to GPU (RTX 3090 Ti) implementations for Bayesian sampling (3 forward passes).
  • Power Efficiency: The FPGA designs consumed <10% of the power of the GPU, resulting in over 100× higher energy efficiency.
  • Comparison with State-of-the-Art: The proposed design outperformed existing CVNN and BayesNN accelerators in terms of accuracy, latency, and power consumption, while uniquely supporting uncertainty estimation.

5. Significance

This work bridges a critical gap in the deployment of reliable AI for complex-valued domains. By proving the theoretical viability of Bayesian CVNNs and providing a practical, automated co-design framework, the authors enable:

• Reliable AI for Critical Systems: Applications like medical imaging and autonomous radar can now assess prediction confidence, reducing risks in safety-critical scenarios.
• Efficient Deployment: The co-design approach demonstrates that the high computational cost of Bayesian inference on complex data can be mitigated through specialized hardware, making real-time deployment on FPGAs feasible.
• Design Automation: The shift from manual, heuristic-based architecture design to automated, constraint-aware evolutionary search sets a new standard for optimizing complex-valued deep learning models.

The code and framework are publicly available, facilitating further research and adoption in the field of complex-valued deep learning.