Tantalum Damascene Coplanar Waveguide Resonators Fabricated Using 300 mm Scale Processes

This paper investigates using a damascene fabrication process to replace lossy native sidewall oxides with a metal/substrate interface in tantalum coplanar waveguide resonators, showing a modest improvement in performance that suggests a reduction in surface participation.

The Gist

The Problem: The "Rusty" Sidewalls of Quantum Computers

Imagine you are building a high-speed, ultra-smooth racetrack for professional racing cars. To make the cars go as fast as possible, the track needs to be perfectly smooth. However, as you build the walls of the track, a thin layer of "rust" (in this case, a microscopic layer of oxygen called native oxide) starts to form on the sides of the walls.

Even though this rust is incredibly thin, it’s bumpy and "sticky." In the world of quantum computing, these tiny bumps act like friction. They soak up the energy that the quantum computer needs to function, causing the "cars" (the quantum bits, or qubits) to slow down and lose their information. This loss of energy is what scientists call "decoherence," and it’s one of the biggest hurdles to building a powerful quantum computer.

The Solution: The "Damascene" Method (The Chocolate Mold Approach)

Usually, scientists build these superconducting circuits by etching lines into a surface—kind of like carving a groove into a piece of wood. The problem is that the moment you carve that groove, the sides of the wood are exposed to the air and immediately start to "rust."

Instead of carving the circuit into the surface, this team used a technique called the Damascene process.

Think of it like making a chocolate bar with a pattern:

1. The Mold: Instead of carving a shape out of a solid block of chocolate, you start with a mold (the silicon substrate) that already has the shapes you want (trenches) carved into it.
2. The Pour: You pour liquid chocolate (the tantalum metal) into the mold. Because the metal is poured into a pre-made hole, it fills the space completely, from the bottom to the top.
3. The Leveling: Once the chocolate is set, you use a special tool (called CMP, or Chemical Mechanical Planarization) to sand down the top until it is perfectly flat.

The Magic Trick: Because the metal is "buried" inside the silicon, the sides of the metal aren't touching the air. They are touching the pristine, clean silicon. By "burying" the metal, they effectively hid the "rusty" sidewalls from the electrical signals, preventing that friction from happening.

What They Found: A Smoother Ride

The researchers tested several versions of this "chocolate bar" approach:

• The "Dirty" Version: Some versions had a layer of "rust" trapped at the bottom of the mold (the "Buried Oxide" devices).
• The "Clean" Version: Other versions were made in a vacuum so no air could get in, creating a "Pristine" interface.

The Result: The "Pristine" versions performed significantly better! They showed about twice the efficiency (quality factor) compared to the versions with trapped oxide. This proves that by changing how we build the structure—moving from "carving" to "pouring"—we can significantly reduce the energy loss that plagues quantum devices.

Why It Matters

If we want to build quantum computers that can solve massive problems (like designing new medicines or cracking complex codes), we need qubits that can hold onto their information for a long time. This paper shows a roadmap for using industrial-scale manufacturing (the same kind used to make computer chips for your phone) to create much cleaner, more efficient "tracks" for quantum information to travel on.

Technical Summary

Technical Summary: Tantalum Damascene Coplanar Waveguide Resonators Fabricated Using 300 mm Scale Processes

Problem Statement

In superconducting quantum computing, specifically within transmon qubit architectures, device performance is heavily limited by energy loss caused by Two-Level Systems (TLS). A primary source of these losses is the presence of native surface oxides at the interfaces of the superconducting material. While previous research has focused on capping the top surface of tantalum (Ta) to mitigate oxidation, the sidewall oxidation—the oxide layer that forms on the vertical edges of etched superconductors—remains a significant and difficult-to-address loss mechanism. This sidewall oxide increases the Surface Participation Ratio (SPR), meaning a larger fraction of the electric field energy resides in lossy dielectric interfaces.

Methodology

The researchers employed a damascene fabrication process to fundamentally change the device geometry. Instead of etching the superconductor and leaving exposed sidewalls, they etched trenches into a silicon (Si) substrate and filled them with metal.

1. Fabrication Flow:

   • Trenching: Using 300 mm scale processes, Si trenches were defined via immersion 193 nm lithography and reactive ion etching (RIE), followed by an anisotropic aqueous hydroxide-based etch to create sloped {111} sidewalls.
   • Interface Engineering: The study compared two distinct interface types:
     • Buried Oxide: A "broken vacuum" approach where a 3 nm ALD TaN seed layer was deposited, the vacuum was interrupted (allowing native oxynitride formation), and then a second TaN layer was deposited.
     • Pristine Interface: A "continuous vacuum" approach where the TaN seed layer and subsequent Ta sputtering were performed in situ without air exposure to prevent oxidation.
   • Planarization: The Ta/TaN stack was filled into the trenches and then leveled using Chemical Mechanical Planarization (CMP). This embeds the superconductor within the pristine silicon, effectively replacing the metal/air sidewall with a metal/substrate interface.
   • Final Exposure: The sacrificial oxide layer was etched away to expose the recessed Ta structures.

2. Characterization:

   • Structural: Scanning Transmission Electron Microscopy (STEM) and Energy Dispersive Spectroscopy (EDS) were used to map elemental abundances (Ta, Si, N, O) at the interfaces.
   • Electromagnetic: COMSOL MultiPhysics was used for resonator simulations.
   • Cryogenic: Resonator performance (internal quality factor $Q_I$, coupling quality factor $Q_C$, and resonance frequency $\omega_0$) was measured in a dilution refrigerator at temperatures from 25 mK to 350 mK across various power levels.

Key Contributions

• Implementation of Damascene for Quantum Devices: Successfully adapted the industrial damascene process (traditionally used for copper interconnects in CMOS) for the fabrication of high-performance tantalum superconducting resonators on 300 mm wafers.
• Sidewall Mitigation Strategy: Demonstrated a method to eliminate the metal/air interface at the device sidewalls by "burying" the superconductor within the substrate.
• Interface Comparative Study: Provided a systematic comparison between "buried oxide" (intentional oxidation) and "pristine" (vacuum-maintained) interfaces using advanced STEM/EDS imaging.

Results

• Interface Verification: STEM/EDS confirmed that "Buried Oxide" devices (A and B) contained trapped oxygen and nitrogen at the Si/Ta interface, whereas "Pristine" devices (C, D, and E) showed no oxide at the Si/Ta interface.
• Quality Factor Improvement: The "Pristine" interface devices showed a statistical improvement in internal quality factor ($Q_I$) of approximately 2$\times$ compared to the "Buried Oxide" devices at -60 dBm.
• TLS Behavior: The devices exhibited standard TLS behavior, including power-dependent saturation and temperature-dependent loss regimes.
• Kinetic Inductance: Experimental resonance frequencies were lower than simulated values, which was successfully reconciled by accounting for the significant contribution of kinetic inductance ($L_{ki}$) in the Ta films.
• Performance Variance: While the pristine interface improved performance, the authors noted significant variance in $Q_I$ across different devices, suggesting that other unmitigated loss mechanisms (beyond the Si/Ta interface) still exist.

Significance

This work represents a significant step toward scalable, high-coherence quantum hardware. By proving that the damascene process can be used to reduce surface participation and mitigate sidewall oxidation, the researchers have provided a roadmap for improving qubit coherence times ($T_1$). Furthermore, the use of 300 mm scale processes aligns superconducting device fabrication with industrial semiconductor manufacturing standards, which is essential for the mass production of large-scale quantum processors.