A Multiplication-Free Spike-Time Learning Algorithm and its Efficient FPGA Implementation for On-Chip SNN Training

Technical Summary: A Multiplication-Free Spike-Time Learning Algorithm and its Efficient FPGA Implementation for On-Chip SNN Training

1. Problem Statement

While Spiking Neural Networks (SNNs) are biologically inspired and offer high energy efficiency through event-driven, sparse computation, performing supervised on-chip training remains a significant hardware challenge. Existing approaches face three primary bottlenecks:

• Computational Overhead: Traditional training methods (like Surrogate Gradient or Backpropagation Through Time) rely heavily on floating-point arithmetic and dense spike trains, which are resource-intensive for edge hardware.
• Memory Constraints: Storing explicit gradients and large weight matrices requires significant memory bandwidth and capacity.
• Hardware Inefficiency: Most current neuromorphic chips (e.g., Loihi, TrueNorth) are optimized for inference but lack robust support for online, supervised learning, forcing a reliance on offline training via GPUs.

2. Methodology

The authors propose a novel framework that unifies a multiplication-free, spike-time-based learning algorithm with a specialized FPGA architecture.

A. Algorithmic Approach:

• Single-Spike Temporal Coding: Information is encoded in the precise latency (timing) of a single spike rather than the firing rate. This maximizes sparsity and minimizes activity.
• Spike-Time-Driven Backpropagation: Instead of calculating complex floating-point gradients, the algorithm encodes gradient information into signed backward spikes.
  • The magnitude of the gradient is represented by the timing of the backward spike.
  • The sign of the gradient is represented by the polarity (positive or negative spikes).
• Multiplication-Free Updates: By converting deltas into spike timings, the weight update process is transformed from multiplication-heavy operations into simple adder-based and bit-shift operations.

B. Hardware Architecture (FPGA):

• Modular Design: The architecture consists of dedicated modules for the Forward Pass (IF neurons, fully connected layers, output decision-maker) and the Backward Pass (Delta calculator, Spike Gradient Generator, and Weight Updaters).
• Semi-Shared Resource Strategy: To minimize the footprint on the Xilinx Artix-7 FPGA, the design reuses adder trees, comparators, and BRAMs across both the forward and backward passes.
• Universal Time Coding: A sparse communication protocol that transmits 4-bit or 5-bit timestamps only when active spikes occur, reducing interconnect bandwidth.
• Fixed-Point Arithmetic: The system uses 12-bit fixed-point weights (Q5.7) and 10-bit fixed-point deltas to balance precision and hardware efficiency.

3. Key Contributions

• Algorithmic Innovation: Developed a supervised learning rule that eliminates the need for floating-point multipliers and explicit gradient storage by utilizing spike latencies.
• Hardware Efficiency: Created a "near-multiplication-free" digital pipeline that maps directly to FPGA logic (LUTs and Flip-Flops), avoiding the heavy use of DSP slices.
• On-Chip Learning Capability: Enabled a fully event-driven, real-time training pipeline that can adapt to new data on-device, bridging the gap between inference-only neuromorphic chips and general-purpose processors.

4. Results

The proposed method was validated through software simulations and hardware implementation on a Xilinx Artix-7 FPGA.

• Accuracy:
  • MNIST: Achieved 96.5% (3-layer) and 97.4% (2-layer), performing comparably to state-of-the-art methods like S4NN and BS4NN.
  • Fashion-MNIST: Achieved 84.8%.
  • 8×8 Digits: Achieved 98.0%.
• Hardware Performance (vs. HaSiST):
  • Resource Utilization: Significantly lower overhead. The backward pass used ~7.4x fewer LUTs and 2x fewer registers per synapse compared to the HaSiST implementation.
  • Frequency: The backward pass achieved 105.3 MHz, a 110.6% improvement over HaSiST (50 MHz), due to the removal of floating-point multipliers.
  • Throughput: Achieved 0.0316 × 10⁹ FeaPS, outperforming HaSiST by approximately 5.47%.

5. Significance

This research provides a practical blueprint for edge intelligence. By proving that supervised learning can be achieved through simple integer additions and spike-timing logic, the authors demonstrate that high-performance, real-time learning is possible on low-power, resource-constrained hardware. This paves the way for autonomous edge devices that can learn and adapt to their environments without needing a connection to a cloud-based GPU server.