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From Mirage to Grounding: Towards Reliable Multimodal Circuit-to-Verilog Code Generation

This paper reveals a critical "Mirage" phenomenon in which multimodal models bypass visual circuit diagrams to generate code solely based on text identifiers, and introduces VeriGround, a 4B-parameter model trained with anonymization and preference alignment to achieve reliable, truly grounded conversion of circuit diagrams to Verilog.

Original authors: Guang Yang, Xing Hu, Xiang Chen, Xin Xia

Published 2026-05-06

📖 5 min read🧠 Deep dive

CC BY 4.0

Original authors: Guang Yang, Xing Hu, Xiang Chen, Xin Xia

Original paper licensed under CC BY 4.0 (http://creativecommons.org/licenses/by/4.0/). ✨ This is an AI-generated explanation of the paper below. It is not written or endorsed by the authors. For technical accuracy, refer to the original paper. Read full disclaimer

The Big Problem: The "Mirage" Effect

Imagine you are taking a test where you must draw a city map based on an image of that city. However, the test instructions also include a list of street names (like "Main Street" and "Oak Avenue").

The researchers discovered that many AI models cheat. Instead of actually looking at the city image to figure out where the streets run, the AI reads the list of street names and simply recites a memorized map it already knows.

The "Mirage" Phenomenon:
The authors call this a Mirage (a Fata Morgana). It is like seeing water in the desert that is not actually there.

The Test: They showed the AI a real circuit diagram (the image) and asked it to write the code (the map).
The Trick: They replaced the real image with a blank white image, but kept the list of street names (the module header) exactly the same.
The Result: Surprisingly, the AI performed just as well with the blank image, sometimes even better!

This proves that the AI did not actually "see" the circuit diagram. It ignored the image entirely and guessed the code based only on the component names. If the names were "Sum" and "Carry," the AI knew it had to build a "Half Adder" without ever looking at the wires in the diagram.

Why This Matters: The Silicon Trap

Why is this important? The paper compares this to building a house.

Normal Code: If a web designer makes a mistake, the website looks ugly. It can be fixed easily.
Circuit Code: If an AI makes a mistake in a circuit diagram, that code is burned onto a physical chip (silicon). Once the chip is manufactured, you cannot undo the mistake with "Ctrl+Z." It is like pouring a concrete foundation and then realizing the door is on the wrong side. You have to tear down the entire building.

If the AI hallucinates (makes things up) based on text clues instead of visual reality, it could create chips that look perfect on paper but fail in the real world.

The Solution: The "Amnesia" Test and a New AI

To fix this, the researchers built two things: a new test and a new AI model named VeriGround.

1. The New Test: "C2VEVAL" (The Amnesia Test)

They created a benchmark where they "anonymized" the test.

Normal Mode: The AI sees the diagram and the names (e.g., "Clock", "Reset").
Anonymized Mode: They changed all names to generic placeholders like "Val_0", "Val_1", and "Val_2".
The Goal: If the AI truly understands the image, it should still work with the generic names. If it only cheated using the names, it should fail.

The Result: When they removed the names, the performance of most large AI models collapsed. This confirmed that the "Mirage" was real. The models actually looked at the image only about 8–9% of the time.

2. The New AI: "VeriGround" (The Honest Student)

The researchers trained a new, smaller AI (only 4 billion parameters, which is tiny compared to giants like GPT-5) to stop cheating. They used three specific training tricks:

Trick A: The "Veiled" Training (Anonymization): They forced the AI to learn from anonymized data. Since it could not rely on the names, it had to learn to read the actual lines and shapes in the diagram.
Trick B: The "Say No" Training (Refusal Augmentation): They taught the AI to say, "I cannot do this," if the image was blank or did not match the instructions. This prevents the AI from guessing when it is unsure.
Trick C: Focus on the "First Impression" (D-ORPO): This is a technical adjustment. When an AI decides to answer or refuse, it makes that decision in the very first words of its response. The researchers made the AI pay special attention to these first few words to ensure it makes the right choice (Generating vs. Refusing) without being confused by the length of the answer.

The Results: Small but Mighty

The new AI, VeriGround, achieved some impressive results:

It actually looks: Under the "anonymized" test (where cheating is impossible), VeriGround scored much higher than all other models, proving it really reads the diagrams.
It does not guess blindly: It learned to reject blank images 92% of the time, yet rarely rejected a valid image (only 1.2% false rejections).
It punches above its weight: Although VeriGround is a "small" model (4B parameters), it performed just as well as the massive, expensive "GPT-5.4" model when names were present, and outperformed it when the names were removed.

Summary

The paper reveals that many AI models are "just pretending" when converting circuit images into code; they only read the labels and ignore the image. The authors built a new test to expose this "Mirage" and trained a new, honest AI (VeriGround) that actually looks at the image, refuses to guess when confused, and performs better on this task than the giants.

Technical Summary: From Mirage to Grounding

1. Problem Definition and the "Mirage" Phenomenon

The work addresses the reliability of Multimodal Large Language Models (MLLMs) in generating Verilog code from circuit schematics, a task requiring the translation of visual schematics into synthesizable Register-Transfer Level (RTL) code. The authors identify a critical, hidden defect termed the Mirage Phenomenon.

Under standard evaluation protocols, MLLMs receive a schematic and a module_header (containing module names, ports, and parameters). The authors demonstrate that many state-of-the-art MLLMs do not genuinely "read" the visual topology. Instead, they leverage identifier semantics within the module_header to retrieve canonical RTL templates.

Evidence: When the schematic is replaced with a blank image (while the module_header is retained), model performance (Pass@k) remains unchanged or even improves.
Implication: High benchmark scores often mask a lack of visual grounding. Models bypass visual input entirely, relying on textual shortcuts. This poses a safety risk in hardware design, where a single misread schematic can silently propagate through the toolchain and cause defects at the silicon level.

2. Methodology

A. Benchmark Construction: C2VEVAL

To quantify the Mirage Phenomenon, the authors compiled C2VEVAL, a benchmark ensuring exact image-code correspondence.

Data Source: 169 samples derived from established Verilog benchmarks (VerilogEval-v2, RTLLM-v2, ResBench, ArchXBench), rendered into schematics using NETLISTSVG.
Coupled Protocol: The benchmark evaluates models under two variants:
1. Normal: Original identifiers in both the diagram and the header.
2. Anony (Anonymized): All semantically loaded identifiers (module names, port names, parameters) are replaced with positional placeholders (e.g., val_0, val_1). The diagram is re-rendered to match these placeholders, removing semantic hints while preserving topology.
Evaluation Modes:
- Original: Real schematic diagram provided.
- Mirage: Diagram replaced with a blank image; header retained.

B. Proposed Solution: VeriGround

The authors propose VeriGround, a 4B-parameter MLLM trained to enforce genuine visual grounding and balance the trade-off between hallucination and excessive refusal. The training pipeline consists of three stages:

Data Collection & Anonymization:
- A large-scale corpus (~54,000 samples) is extracted from GitHub, verified for synthesis, and filtered by difficulty.
- The corpus is split into Normal and Anony variants, forcing the model to learn from visual topology rather than memorizing identifiers.
Mixed Supervised Fine-Tuning (SFT):
- The model is fine-tuned on the mixed Normal + Anony corpus. This forces the model to anchor predictions in the visual structure of the schematic rather than relying on semantic shortcuts in the header.
Decision-Oriented ORPO Alignment (D-ORPO):
- To address the tendency of models to either hallucinate code without visual input or excessively reject valid inputs, the authors introduce D-ORPO.
- Preference Pairs: Three categories are constructed:
  - MATCH: Valid diagram + Refusal (rejected) vs. Correct code (chosen).
  - BLANK: Empty image + Code (rejected) vs. Refusal (chosen).
  - MISMATCH: Unrelated diagram + Code (rejected) vs. Refusal (chosen).
- Mechanism: Standard ORPO treats all tokens equally, causing the model to lean towards shorter refusal words due to length asymmetry. D-ORPO weights the first $K$ response tokens (the decision boundary) with a weight $\alpha > 1$ . This concentrates the preference signal on the Generate-or-Refuse decision, mitigating excessive refusal while maintaining high refusal rates for invalid inputs.

3. Main Contributions

Phenomenon Identification: The work documents that the Mirage Phenomenon is universal across eight evaluated MLLMs (including GPT-5.4, Opus-4.6, and open-source models). In Normal mode, removing the diagram often leads to better results; genuine visual grounding accounts for only about 8–9% of samples.
Benchmark & Evaluation: C2VEVAL introduces a coupled Normal/Anony × Original/Mirage protocol that isolates identifier semantics as the primary driver of performance and serves as a diagnostic for Vision-to-Code pipelines.
Methodology: VeriGround (4B) integrates identifier anonymization, refusal augmentation, and D-ORPO alignment.
Performance: VeriGround achieves a Functional Pass@1 of 46.11% (Normal) and 42.51% (Anony).
- It approaches the performance of GPT-5.4 (45.51%) under Normal conditions.
- It significantly outperforms all baselines under Anony conditions (e.g., +31.13% over Opus-4.6), confirming genuine visual grounding.
- It maintains a False Refusal Rate (FRR) of only 1.20% (Normal) and 0.00% (Anony), while the refusal rate for blank images exceeds 92%.

4. Results and Significance

Visual Grounding vs. Shortcuts: The empirical study shows that under the Anony protocol, the "Mirage advantage" (where blank images yield better results) reverses for 7 out of 8 models. This confirms that standard high performance is largely driven by header-based shortcuts rather than visual understanding.
Efficiency: VeriGround, with only 4 billion parameters, rivals frontier proprietary models (e.g., GPT-5.4, estimated ~200B+) in Normal mode and clearly surpasses them in Anony mode.
Balancing: The D-ORPO component successfully resolves the tension between hallucination and excessive refusal. Standard ORPO achieved near-perfect refusal for blank images but suffered from high false refusal rates (~9%) on valid inputs. D-ORPO reduced the FRR to near zero while maintaining high refusal accuracy for invalid inputs.
Generalizability: The authors claim the methodology (Anonymization + Refusal Augmentation + Decision-Oriented Alignment) is transferable to other Vision-to-Code tasks (e.g., UI-to-HTML, Diagram-to-Python), where textual prompts may reveal semantic shortcuts.

5. Claims and Limitations

The work posits that VeriGround offers a transferable solution for calibrating hallucination and excessive refusal in AI code generation. It does not claim to solve all challenges in hardware design but rather provides a rigorous evaluation framework and training recipe to ensure models rely on visual evidence.

Threats to Validity: The authors acknowledge that C2VEVAL is limited to 169 samples and specific schematic categories. Results may not fully generalize to VHDL, SystemVerilog, or industrially scaled schematics. Furthermore, functional correctness relies on testbench simulations, which may not cover all edge cases.
Future Work: The authors plan to scale VeriGround to larger and smaller architectures and expand the benchmark with industrially scaled schematics to further validate the generalizability of their approach.