Sub-kelvin thermal conductivity of substrates and on-chip routing in quantum integrated systems

This study experimentally characterizes the sub-kelvin thermal conductivity of various substrate materials and on-chip routing, revealing that high-resistivity silicon offers superior thermal performance and that while routing lines enhance in-plane conductance, the substrate remains the dominant heat path, thereby emphasizing the critical importance of material selection and 3D integration for effective thermal management in large-scale quantum systems.

The Gist

Imagine you are trying to build a super-fast, ultra-sensitive computer that only works when it is colder than outer space. This is a quantum computer. To make it work, you need to cram millions of tiny electronic switches (qubits) and their "brain" (control electronics) right next to each other on a single chip.

But here's the problem: The "brain" gets hot, even when it's freezing cold. If that heat leaks over to the sensitive switches, the computer breaks. The scientists in this paper asked a simple question: "What happens to heat when it travels through the materials we use to build these chips at near-absolute-zero temperatures?"

Here is what they found, explained with some everyday analogies.

1. The Highway vs. The Dirt Road (Substrate Materials)

The "substrate" is the base material the chip sits on, like the foundation of a house. The team tested four different foundations:

• High-Resistivity Silicon: Think of this as a super-highway. At these freezing temperatures, heat (which travels as tiny vibrations called "phonons") zooms through this material very easily. It's the best at moving heat away.
• Low-Resistivity Silicon: This is like a dirt road full of potholes. Because this silicon has extra "impurities" (dopants) added to it for electrical reasons, those impurities act like speed bumps. They crash into the heat vibrations, slowing them down drastically. It's about 100 times worse at moving heat than the high-resistivity version.
• Sapphire & Borosilicate Glass: These are like narrow, bumpy trails. They conduct heat, but not as well as the silicon highway. Interestingly, the sapphire trail was surprisingly bumpy (due to tiny internal crystal defects), making it worse at conducting heat than you might expect for such a hard material.

The Takeaway: If you want to move heat away quickly, use the "highway" (High-Resistivity Silicon). If you want to keep heat trapped in one spot to protect a neighbor, use the "dirt road" (Low-Resistivity Silicon).

2. The Metal Wires (On-Chip Routing)

The team also looked at the wires (routing) that connect the different parts of the chip. They used superconducting wires (Niobium), which are like magic pipes that carry electricity without resistance.

They wanted to see if these wires would act as a "heat shortcut," stealing heat from the electronics and dumping it onto the qubits.

• The Result: The wires did help move heat a little bit (about 4 times more than the silicon alone in their specific test setup).
• The Catch: In a real, thick chip, the base material (the substrate) is so much bigger than the thin wires that the substrate still does 99% of the work. The wires are like a small side-stream; the substrate is the main river.

3. The "Microwatt" Problem

The most critical finding is about how little heat it takes to cause trouble.
The scientists found that at these super-cold temperatures, you only need a tiny amount of power (measured in nanowatts—billionths of a watt) to raise the temperature of the chip enough to mess up the quantum calculations.

• The Analogy: Imagine trying to keep a block of ice frozen in a room. If you light a single match (the heat from the electronics), the ice melts instantly.
• The Reality: Current electronic chips generate heat like a bonfire compared to what these quantum chips can tolerate. Even though the electronics are only a few millimeters away, the heat they generate is enough to destroy the quantum state.

The Big Conclusion

You cannot just stick the "brain" and the "sensitive switches" on the same flat piece of silicon and hope for the best. The heat will travel too easily (or too unpredictably) and ruin the experiment.

The paper suggests that the solution is 3D stacking (like a skyscraper instead of a bungalow). You need to separate the hot electronics from the cold switches using special "thermal insulation" layers or by placing them on different levels, so the heat from the brain doesn't accidentally cook the switches.

In short: At near-absolute zero, heat behaves very differently. The materials we choose act like either super-highways or bumpy dirt roads for heat, and we need to be extremely careful about where we put our heat sources, or the whole system will overheat and fail.

Technical Summary

Technical Summary: Sub-kelvin thermal conductivity of substrates and on-chip routing in quantum integrated systems

Problem Statement
The transition to fault-tolerant quantum computers requires scaling to millions of physical qubits, necessitating the close integration of heterogeneous components such as qubits and classical cryogenic control electronics (cryo-CMOS). Current architectures, whether System-on-Chip (SOC) or 3D System-in-Package (SIP), face a critical thermal management bottleneck. The heat dissipated by cryo-CMOS (typically several microwatts per qubit) introduces decoherence sources that degrade qubit lifetimes. While thermal transport in bulk materials is well-documented at room temperature, systematic experimental data in the sub-kelvin regime is scarce. Furthermore, thermal transport at these temperatures is governed by phonon propagation and is exquisitely sensitive to crystalline purity, sample dimensions, and surface properties, making room-temperature values unreliable for extrapolation. Understanding the thermal properties of fundamental building blocks—specifically substrates and on-chip routing—is a prerequisite for designing large-scale quantum processors with optimized thermal management.

Methodology
The authors conducted an experimental thermal study in two phases:

1. Substrate Characterization:

   • Materials: Four substrate materials commonly used in semiconductor and quantum technologies were tested: High-Resistivity (HR) Silicon (Float-Zone), Low-Resistivity (LR) Silicon (Czochralski, Boron-doped), Borosilicate glass, and Sapphire.
   • Setup: Samples were mounted on a copper plate within a dilution refrigerator. A heater and a RuO2 thermometer were attached to the "hot" end of the suspended sample, while the "cold" end was thermally anchored to the mixing chamber.
   • Measurement Protocol: Heating power ($Q$) was applied in steps (nanowatts to microwatts) at base temperatures ($T_0$) of 50 mK and 300 mK. The resulting temperature rise ($T_h$) was measured to determine effective thermal conductivity ($\kappa$) using steady-state heat conduction definitions.
   • Validation: A control experiment with a second thermometer on the cold side verified that the substrate/copper interface did not act as a thermal bottleneck, ensuring the measured resistance was dominated by the substrate itself.
   • Analysis: Phonon mean free paths (MFP) were extracted using a finite-element non-equilibrium Green's function (FENEGF) approach to evaluate ballistic conductance and identify dominant scattering mechanisms.

2. On-Chip Routing Evaluation:

   • Test Vehicle: A planar device was fabricated on an LR silicon substrate featuring superconducting Niobium (Nb) routing lines and Gold (Au) pads.
   • Modification: To isolate the thermal contribution of the routing, the silicon substrate beneath the routing was back-etched to a residual thickness of 50 µm, creating a "membrane" to minimize the parallel thermal path of the bulk silicon.
   • Measurement: Thermal conductance was measured between two sections of the routing line at $T_0 = 50$ mK and $300$ mK, comparing the results against the expected conductance of the silicon substrate alone.

Key Results

• Substrate Thermal Conductivity (at 300 mK):

  • HR Silicon: Exhibited the highest conductivity at $5 \cdot 10^{-2}$ W/m·K, following a $T^{2.4}$ dependence. MFP analysis indicated transport is limited by Casimir-type boundary scattering (MFP $\approx$ 4000 µm).
  • LR Silicon: Showed a two-order-of-magnitude reduction to $8 \cdot 10^{-4}$ W/m·K with a $T^{2.2}$ dependence. The reduced MFP ($\approx$ 30 µm) and $T^{-3/2}$ scaling were attributed to phonon-hole scattering caused by boron doping and oxygen impurities.
  • Sapphire: Measured at $2 \cdot 10^{-3}$ W/m·K ($T^3$ dependence). Despite the $T^3$ scaling typical of crystals, the absolute magnitude was significantly lower than bulk values, and the MFP ($\approx$ 50 µm) was far below the Casimir limit, suggesting structural disorder (grain boundaries) limits transport.
  • Borosilicate: Measured at $2 \cdot 10^{-3}$ W/m·K with a $T^2$ dependence, characteristic of amorphous solids where transport is described by tunneling two-level systems rather than boundary scattering.

• On-Chip Routing Impact:

  • The inclusion of Nb routing lines increased the in-plane thermal conductance of the test vehicle by a factor of four compared to the LR silicon substrate alone.
  • However, the study notes that this enhancement was only measurable because the substrate thickness was artificially reduced to 50 µm. In a standard SOC architecture where the substrate retains its full thickness (hundreds of micrometers), the substrate remains the dominant heat path, and the routing contribution is negligible.

• Thermal Constraints:

  • Measurable temperature gradients were established with applied powers as low as 1–10 nW.
  • The authors estimate that for centimeter-scale dies, the tolerable power dissipation before significantly perturbing qubit temperatures is on the order of tens of nanowatts at 300 mK. This is far below the microwatt-level dissipation of current cryo-CMOS.

Significance and Claims
The paper claims to provide quantitative guidance for substrate selection in cryogenic quantum systems. The results highlight that no single substrate optimally fulfills all requirements; for instance, LR silicon offers better thermal isolation for qubits, while HR silicon facilitates heat removal for dissipative control dies.

Crucially, the work underscores that in planar SOC architectures where qubits and control electronics share the same substrate, the thermal crosstalk is severe. The authors conclude that the current level of power dissipation in cryo-CMOS makes co-integration on the same substrate thermally unviable without significant mitigation. Consequently, the paper advocates for function partitioning through 3D integration and System-in-Package (SIP) approaches. These architectures allow for the placement of control circuits in close proximity to qubits while utilizing thermal decoupling strategies (such as 3D interconnects or thermally resistive substrates) to manage heat flow, rather than relying solely on planar thermal isolation.