Emerging 2D Materials for Beyond von Neumann Computing: A Perspective

This perspective argues that overcoming the von Neumann bottleneck requires the next decade of 2D materials research to shift from isolated record-breaking devices to the integrated coexistence of graphene transistors, memristors, and photonic structures on a single semiconductor wafer to enable in-memory and optical computing.

The Gist

The Big Problem: The Traffic Jam

Imagine a super-fast factory (the computer processor) that builds things, and a massive warehouse (the memory) that stores the raw materials. In our current computers, the factory and the warehouse are in different buildings. Every time the factory needs a part, a truck has to drive back and forth between them.

For decades, we made the factory faster and the trucks smaller. But now, the factory is so fast that the trucks can't keep up. The factory sits idle, waiting for the trucks to arrive. This is called the "von Neumann bottleneck." The paper argues that we can't just build faster trucks; we need to redesign the whole factory so the workers can build things right where the materials are stored.

The Solution: The "Swiss Army Knife" Material

The author suggests using 2D materials (ultra-thin sheets of atoms, like graphene) to fix this. Think of these materials not as a single tool, but as a Swiss Army Knife that can do three very different jobs at once, all on the same tiny piece of silicon:

1. The Logic Switch (The Factory Worker):

   • The Problem: Pure graphene is like a highway with no exits; electricity flows through it too easily to act as an on/off switch for digital logic.
   • The Fix: The paper suggests cutting graphene into very narrow strips called nanoribbons. Imagine cutting a wide highway into a narrow alleyway. This forces the electricity to behave like a switch (on/off), allowing us to build transistors that are smaller and faster than anything we can make with silicon today.

2. The Memory/Brain Cell (The Smart Warehouse):

   • The Problem: Current memory is either "on" or "off" (like a light switch), but our brains and advanced AI need to remember things in shades of gray (like a dimmer switch).
   • The Fix: By stacking 2D materials with special oxides, we can create memristors. These are like "smart sticky notes" that can hold a specific level of resistance. They can store data and do math at the same time. The paper claims these can be tuned to hold many different levels of information, which is crucial for training AI.

3. The Light Beam (The Messenger):

   • The Problem: Moving data with electricity generates heat and hits speed limits.
   • The Fix: 2D materials can also act as light emitters. Imagine a layer of graphene that, when you apply a tiny voltage, glows with a specific color of infrared light. This allows the computer to send information using light beams instead of electric wires, which is faster and cooler.

The "Grand Challenge": Putting the Puzzle Together

The paper makes a very specific claim: We already have the pieces, but we haven't built the puzzle.

• The Past Decade: Scientists have spent ten years proving that these 2D materials work individually. They have shown that a graphene transistor works, a 2D memory cell works, and a 2D light emitter works.
• The Next Decade: The author argues that the winner won't be the person who makes the best single piece. The winner will be the first team to glue all three pieces together on a single chip (a single wafer) without breaking them.

Think of it like building a car. We have great engines, great tires, and great steering wheels. But we haven't successfully built a car where all three parts are manufactured and assembled in the same factory line. The paper says the next big breakthrough is integration—making sure these three different technologies can live together on one tiny chip.

Why This Matters

If we succeed, we get a computer that:

• Doesn't waste energy moving data back and forth.
• Processes information like a human brain (using events and spikes rather than a rigid clock).
• Uses light to communicate internally, making it incredibly fast.

The paper concludes with a roadmap: The technology is ready. The next five years are about solving the engineering puzzle of putting these three "Swiss Army Knife" functions onto one single chip to create the next generation of super-computers.

Technical Summary

Technical Summary: Emerging 2D Materials for Beyond von Neumann Computing

Problem Statement
The paper identifies a structural bottleneck in modern computing: the von Neumann partition between memory and logic. While Dennard scaling has historically improved compute density, the widening gap between memory bandwidth and arithmetic throughput has rendered data movement the primary energy consumer, a trend exacerbated by increasing model sizes. Conventional bulk silicon cannot natively provide the specific device characteristics required for three emerging architectural responses: in-memory/resistive computing, neuromorphic/event-driven processing, and integrated photonics. Specifically, there is a lack of tunable, high-mobility channels at sub-10 nm pitches, non-volatile analog-programmable conductances, and on-chip optical elements with reconfigurable spectral response.

Methodology and Scope
This perspective surveys the convergence of three specific thrusts within the two-dimensional (2D) materials community, arguing that 2D materials offer a unified substrate to address the aforementioned architectural needs. The analysis relies on:

1. Device Modeling and Characterization: Utilizing atomistic non-equilibrium Green function (NEGF) modeling for graphene nanoribbons (GNRs) and multiphysics simulations for oxide memristors to understand transport limits, switching dynamics, and variability.
2. Comparative Analysis: Benchmarking 2D-material-based primitives against established beyond-CMOS options (Phase-Change Memory, Ferroelectric FETs, STT-MRAM) across energy, density, endurance, analog precision, and photonic capability.
3. System-Level Integration Argument: Proposing a "co-design" approach where algorithmic training procedures are explicitly budgeted for analog non-idealities (e.g., conductance drift, noise) and where the unit of evaluation shifts from isolated device metrics to complete device-plus-mapping-plus-training stacks.

Key Contributions and Technical Findings

• 2D Channels (Graphene and GNRs): While pristine graphene is a semimetal unsuitable for digital logic, patterning it into nanoribbons (GNRs) opens a width-dependent bandgap. NEGF modeling indicates that GNRs with widths of 1–3 nm can achieve bandgaps comparable to InGaAs while retaining mobility advantages. However, performance is limited by line-edge roughness (where ~0.5 nm RMS roughness significantly degrades on-current) and dielectric integration. High-k dielectrics (HfO2, Al2O3) deposited via atomic layer deposition are critical for preserving transport and achieving sub-1 nm equivalent oxide thickness. Beyond logic, scaled GNR FETs are identified as viable on-chip thermometers for dense temperature monitoring.
• Resistive Switching and Memristors: The paper argues that the challenge for hardware machine learning is no longer the existence of resistive switching, but the precision of conductance trajectories and retention. 2D materials serve two roles here: as ultrathin tunneling barriers (e.g., hexagonal boron nitride, TMDs) to suppress current creep and improve linearity, and as electrodes (graphene) to confine filaments and reduce parasitic capacitance. The authors emphasize that variability must be treated as a first-class design parameter, advocating for the reporting of full conductance distributions and bit-error-rate trajectories rather than just median figures of merit.
• Neuromorphic Circuits: The paper highlights the potential of hybridizing standard CMOS with beyond-CMOS primitives. Specifically, replacing comparator stages in integrate-and-fire (IF) neurons with side-contacted field-effect diodes (S-FEDs) can reduce per-spike energy and silicon area while maintaining compatibility with digital design flows.
• Photonic and Thermal Primitives: Multilayer graphene stacks are presented as electrically tunable mid-infrared emitters. By using aperiodic stacking sequences (e.g., Cantor or Fibonacci), these structures can generate switchable, narrowband thermal emission. This capability supports optical neural network activation functions and on-chip thermal signaling, providing a native optical-electronic interface that all-electronic platforms lack.
• Comparative Landscape: A comparative table (Table 1) positions 2D materials not as the superior option on any single metric (e.g., PCM or FeFETs may offer better endurance or density individually), but as the only family capable of spanning the full set of compute primitives, including the native photonic mode. The strategic advantage is argued to be in integration cost and the ability to co-fabricate heterogeneous components on a single wafer.

Results and Proposed Demonstrator
The paper does not present new experimental data but synthesizes existing progress to propose a concrete near-term demonstrator. This hypothetical chip would integrate four distinct blocks on a single CMOS-compatible substrate:

1. Digital Control: Scaled GNR FETs for high-mobility logic and on-chip thermometry.
2. Compute Core: A 2D-stabilized memristive crossbar for in-memory matrix-vector multiplication.
3. Spiking Front-end: S-FED-based neurons for event-driven preprocessing.
4. Photonic Readout: Aperiodic multilayer graphene emitters for tunable mid-infrared inter-chip interconnects.

The paper notes that while each block has been demonstrated separately, no team has yet integrated them on a single wafer with acceptable yield and thermal budget.

Significance and Claims
The central argument of the perspective is that the 2D materials community has spent the last decade producing record-breaking individual devices. The next decade's progress will be determined by the ability to integrate these three distinct thrusts (transistors, memristors, and photonics) onto a single semiconductor wafer.

The paper claims that the "rate-limiting step" is no longer material growth or device physics, but the engineering challenge of integration. It posits that a 2D-material-based heterogeneous chip, despite potentially losing on individual cell metrics compared to specialized non-2D technologies, will outperform systems that bolt together disparate technologies (PCM, FeFET, silicon photonics) from separate process flows due to lower integration costs and superior co-design capabilities.

The authors conclude by outlining a five-year roadmap (2026–2031) with specific, measurable milestones for channel scaling, synapse stability, and photonic integration, urging the field to shift focus from isolated device optimization to system-level convergence.