Spintronic Neuromorphic Hardware Using Domain Wall Based Neurons and Quantized Synapses

Technical Summary: Spintronic Neuromorphic Hardware Using Domain Wall Based Neurons and Quantized Synapses

Problem Statement
The implementation of Artificial Neural Networks (ANNs) on traditional hardware is hindered by the von Neumann bottleneck, characterized by energy-intensive and latency-prone data transfer between memory and processing units. While emerging non-volatile memory (eNVM) devices like spintronics offer ultrafast dynamics, low power consumption, and high endurance, a significant challenge remains in mimicking the analog nature of biological synapses. Magnetic Tunnel Junctions (MTJs) typically offer binary states suitable for digital memory but lack the continuous adjustability required for synaptic weights. Furthermore, the stability of Domain Wall (DW) positions is critical for reliable inference; stray fields or demagnetization can displace DWs, degrading synaptic weight stability and inference accuracy. There is a need for a well-defined, stable, and controllable DW-based neuromorphic hardware model that can accurately emulate both neuron activation and synaptic memory without requiring complex online training on resource-constrained edge devices.

Methodology
The authors propose a fully connected ANN architecture utilizing Heavy Metal/Ferromagnet (HM/FM) heterostructures to emulate both neurons and synapses via micromagnetic simulations.

• Device Simulation: The study numerically solves the Landau-Lifshitz-Gilbert-Slonczewski (LLGS) equation using the Object-Oriented Micromagnetic Framework (OOMMF) and UBERMAG.
• Neuron Emulation: A rectangular HM/FM nanotrack (512 nm × 64 nm × 2 nm) is used to mimic the ReLU activation function. A current pulse (3 ns) applied along the heavy metal layer generates Spin-Orbit Torque (SOT) via the Spin-Hall effect, driving a transverse Domain Wall (DW). The DW position, detected by an MTJ-like structure spanning 128 nm to 384 nm, encodes the conductance. The device is designed to exhibit zero conductance for negative inputs and linear conductance for positive inputs, effectively bypassing the "dead neuron" problem associated with sigmoid functions.
• Synapse Emulation: A larger HM/FM nanotrack (1500 nm × 150 nm × 2 nm) features symmetric, semicircular notch-type corrugations (5 or 10 notches) acting as engineered pinning sites. A 10 ns current pulse with varying current density drives the DW. The notches create localized energy barriers, causing the DW to exhibit step-like motion with temporary pauses (pinning) at specific locations. The electrical conductance at these pinned states serves as discrete, stable synaptic weights.
• Network Training and Quantization: The authors first train a fully connected ANN (784 input, 128 hidden, 10 output nodes) on MNIST and Fashion-MNIST datasets using PyTorch with standard float32 (FP32) weights. Subsequently, these weights are quantized to match the discrete conductance levels achievable by the proposed synapse devices. A "fine-tuning" phase retrains the network using these quantized weights to recover performance losses.

Key Contributions

1. Hardware-Efficient Neuron Model: The demonstration of a DW-based device that accurately mimics the ReLU activation function using a 3 ns current pulse, providing a hardware-friendly alternative to complex activation circuits.
2. Engineered Synaptic Stability: The introduction of lithographically defined, symmetric notches to create controlled pinning centers. This design ensures DW stability against stray fields and enables the creation of discrete, quantized conductance states that function as reliable synaptic weights.
3. Synaptic Memory and Adaptability: The observation of a threshold-dependent delay effect where depinning events are influenced by previous states. This behavior successfully mimics the memory and plasticity inherent in biological synapses.
4. Quantized Neural Network (QNN) Validation: The successful implementation of a fully connected QNN where trained FP32 weights are mapped to discrete DW pinning states. The study validates that fine-tuning the network after quantization can restore accuracy to near-baseline levels.

Results

• Device Performance:
  • The neuron device demonstrated a normalized conductance vs. current density curve closely matching the ReLU function, with a slight deviation corrected via polynomial fitting.
  • The synapse device exhibited step-like DW motion. For a 5-notch system, the DW stabilized at notches with increasing current densities (e.g., 0.500 × 10¹² A/m² for the first notch). A 10-notch system showed similar behavior but required lower current densities to fully switch the magnetization compared to the 5-notch system.
• ANN Accuracy:
  • Baseline (FP32): The network achieved ~97.41% accuracy on MNIST and ~86.40% on Fashion-MNIST.
  • Pure Quantization: Directly mapping weights to discrete levels resulted in ~94.67% (MNIST) and ~62.20% (Fashion-MNIST) accuracy. The significant drop in Fashion-MNIST performance was attributed to the dataset's complex, ambiguous nature (e.g., similar-looking clothing items) and the sparsity of the quantized weight distribution.
  • Fine-Tuned Quantization: Retraining the network with quantized weights restored accuracy to ~97.17% (MNIST) and ~86.22% (Fashion-MNIST), effectively recovering the performance loss seen in pure quantization.
• Confusion Matrix Analysis: The study noted that misclassifications in the Fashion-MNIST dataset were primarily due to inter-class ambiguity (e.g., confusing "Shirt" with "T-shirt/top"), which was exacerbated by quantization but mitigated by fine-tuning.

Significance
The paper claims that engineered DW pinning-depinning dynamics offer a scalable and adaptive pathway for neuromorphic computing. By utilizing geometric constraints (notches) to control DW motion, the authors demonstrate a method to create stable, non-volatile synaptic weights that are robust against displacement. The work bridges the gap between fundamental spintronic magnetization switching and practical neuromorphic architectures, proving that DW-based devices can support complex algorithmic requirements with high computational fidelity. The ability to fine-tune quantized networks suggests that such hardware can be effectively deployed for edge computing applications where low memory footprint and energy efficiency are paramount, without sacrificing inference accuracy.