Technical Summary: UniRTL

Problem Statement

Developing effective representations for Register Transfer Level (RTL) designs is critical for accelerating the hardware design workflow, particularly for tasks like performance prediction and code retrieval. Existing approaches typically rely on a single data modality: either the RTL source code or a graph-based representation (such as a Control Data Flow Graph, CDFG). This unimodal reliance limits the expressiveness and generalization ability of learned representations. While code explicitly encodes semantic and functional information, graph modalities capture critical structural relationships often opaque in code. Furthermore, prior multimodal attempts in the software domain (e.g., GraphCodeBERT) or hardware domain (e.g., CircuitFusion) suffer from weak alignment strategies, incomplete graph representations (omitting operators and control flow), or coarse-grained fusion mechanisms that fail to fully leverage the complementary nature of code and graph data.

Methodology

The authors propose UniRTL, a multimodal pretraining framework designed to learn unified RTL representations by jointly leveraging RTL code and CDFGs. The methodology is built upon three core components:

1. Dataset Construction

The framework utilizes a dataset of 132,008 RTL designs collected from sources including RTLCoder, MG-Verilog, DeepRTL, and DeepCircuitX. These designs are paired with functional summaries. To generate CDFGs, designs are compiled into RTL Intermediate Language (RTLIL) using Yosys, parsed into Abstract Syntax Trees (ASTs) via Stagira, and traversed to extract CDFGs. While 38,888 designs were successfully converted into CDFGs, the remaining noisy samples (which failed conversion) are retained for text-code alignment to maximize data utilization.

2. Model Architecture

UniRTL employs a unified Transformer architecture (based on CodeBERT-base-mlm) to integrate different modalities, avoiding the complexity of modality-specific encoders.

• Graph-Aware Tokenizer: Unlike prior work that flattens variable nodes, UniRTL introduces a specialized tokenizer combining a Graph Isomorphism Network (GIN) and a lightweight Transformer. This tokenizer encodes node types, widths, and textual descriptions, capturing both local structural dependencies and global contextual information within the CDFG.
• Hierarchical Training Strategy:
  • Pretraining: The graph-aware tokenizer is first pretrained using structure-aware masked node modeling and edge prediction.
  • Text-Code Alignment: Before incorporating graph data, the model undergoes a warm-up stage aligning functional summaries (text) and RTL source code using mutual masked modeling. This maximizes data utilization given the abundance of text-code pairs.
  • Graph Incorporation: Finally, graph information is integrated. The model employs mutual masked modeling to achieve fine-grained cross-modal alignment. In this stage, masked tokens in the text and code are recovered using context from the other modalities, and masked graph nodes are recovered using context from the text and code. Global positional encodings derived from the graph Laplacian are added to preserve topological structure.

Key Contributions

• Unified Multimodal Framework: UniRTL is the first framework to jointly leverage RTL code and complete CDFGs for representation learning, addressing the limitations of unimodal approaches.
• Fine-Grained Alignment: Through mutual masked modeling, UniRTL achieves fine-grained alignment between code and graph, surpassing the coarse-grained contrastive learning used in prior works like CircuitFusion.
• Complete Graph Representation: The framework utilizes CDFGs that preserve complete design information (including operators and control flow) and can be faithfully converted back to code, unlike simplified data flows or register-level sub-circuits used in previous studies.
• Hierarchical Training: The strategy of pretraining a graph-aware tokenizer and performing text-code alignment prior to graph integration optimizes data utilization and model performance.

Experimental Results

UniRTL was evaluated on two downstream tasks under multiple settings:

1. Performance Prediction: The model predicted post-synthesis area and delay, both with and without netlist information.

   • Results: UniRTL consistently outperformed all baselines, including StructRTL, VeriDistill, DeepRTL2, and GraphCodeBERT, across all metrics (MAE, MAPE, R2, RRSE).
   • Ablation: Removing the graph component significantly degraded performance, confirming the necessity of structural information. Removing the code component caused a slight drop, indicating complementary value.
   • Netlist Integration: Even when incorporating netlist information via knowledge distillation (using a teacher model trained on netlists), UniRTL achieved state-of-the-art results.

2. Code Retrieval: The model was tested on Natural Language Code Search and Functionality Equivalence Checking.

   • Results: UniRTL achieved the highest F1 scores in Natural Language Code Search and the highest Average Precision (AP) in Functionality Equivalence Checking, outperforming general-purpose embedding models and specialized RTL models.
   • Ablation: The "UniRTL (w/o graph)" variant performed significantly worse than the full model in code search, highlighting the importance of graph information for semantic understanding.

Significance and Claims

The paper claims that UniRTL establishes a more robust and powerful foundation for advancing hardware design automation. By integrating complementary modalities through fine-grained alignment, UniRTL overcomes the expressiveness limits of single-modality approaches. The authors emphasize that their approach provides a comprehensive understanding of RTL designs, enabling instant feedback on quality metrics and efficient design module reuse. The work is presented as a step toward more effective retrieval-augmented generation (RAG) systems for RTL code generation and more accurate performance estimation without relying on time-consuming logic synthesis.

The authors note limitations, including reliance on successful CDFG conversion, current restriction to Verilog, and evaluation under fixed synthesis settings. They identify extending the framework to other hardware description languages, larger industrial designs, and diverse synthesis flows as important future work.