A High-Precision Clock Synchronization System for the CEPC Accelerator

This paper presents an enhanced White Rabbit-based clock synchronization system for the CEPC accelerator that achieves a measured end-node precision of 7.30 ps under temperature variations, significantly surpassing the required 30 ps synchronization budget through architectural improvements including a Si5345A DSPLL, reduced restart uncertainty, and reinforcement learning-based PID control.

The Gist

Imagine a massive, 100-kilometer-long underground racetrack where tiny particles (electrons and positrons) race around at nearly the speed of light. To keep these particles in a tight, perfect bunch and make them collide exactly where scientists want them to, every single control station along the track needs to be synchronized to the same "heartbeat."

This heartbeat is a clock signal. The challenge? The track is so long, and the physics so precise, that if two stations are even a tiny fraction of a second out of sync, the experiment fails. The goal for this project (the CEPC accelerator) was to keep all 192 stations perfectly synchronized within 30 picoseconds.

To put that in perspective: A picosecond is to a second what a second is to about 32 years. It is an almost unimaginably small amount of time.

Here is how the team solved the problem, explained simply:

1. The Problem: The "Old Way" Was Too Noisy

The team started with a standard system called "White Rabbit," which is like a high-tech walkie-talkie network that keeps clocks in sync. However, they found that the standard system had a "noisy engine."

• The Analog Noise: The old system used a mix of digital chips and analog knobs (like a volume dial) to adjust the clock speed. This was like trying to tune a radio by turning a rusty, wobbly knob while standing next to a loud fan. The "knob" (analog circuit) introduced too much static noise, making the clock jittery.
• The Restart Glitch: Every time the system was turned off and on again (like rebooting a computer), the clocks would wake up slightly confused. They would take a "guess" at what time it was, leading to a big jump in error (up to 88.8 picoseconds) before settling down.

2. The Solution: A Digital "Smart Engine"

To fix the noise, the team replaced the old "rusty knob" system with a brand-new, all-digital engine called the Si5345A.

• The Metaphor: Instead of a human turning a wobbly analog dial, imagine a super-precise robot arm that can move in steps so small they are invisible to the naked eye. This new chip generates the clock signal entirely inside its own digital brain. It doesn't need external analog parts, so it's immune to electrical "static" and power fluctuations.
• The Result: This removed the biggest source of noise, making the clock signal incredibly smooth and stable.

3. The Fix for the "Restart Confusion"

To stop the clocks from getting confused when they restart, the team wrote a new "wake-up routine" in the software (firmware).

• The Metaphor: Imagine a choir of 192 singers. In the old system, when they started singing again after a break, everyone started on a slightly different beat, and it took a while to find the right rhythm.
• The New Routine: The new system forces every singer to check their position against a master conductor immediately upon waking up. If they are even a tiny bit off, the system resets them and tries again until they are perfectly aligned.
• The Result: The "waking up" error dropped from a huge 88.8 picoseconds down to a tiny 12 picoseconds.

4. The "Conductor" for the Whole Orchestra

With 192 stations spread over 100 km, simply having good individual clocks isn't enough. If Station A is slightly off, Station B (which listens to A) will be even more off, and Station C even more so. This is called "cascading error."

• The Old Way: Each station tried to fix itself independently. Sometimes they over-corrected; sometimes they under-corrected.
• The New Way: The team built a "Global Conductor" (a computer program) that listens to all 192 stations at once.
  • Temperature Compensation: Clocks drift when they get hot or cold. The system measures the temperature of every station and automatically adjusts the clock speed to cancel out the heat, like a thermostat that knows exactly how much to cool the room.
  • AI Learning: To figure out the perfect settings for this conductor, they used a type of Artificial Intelligence (Reinforcement Learning). The AI played a game where it tried to get all the clocks to sync up. Once it learned the best strategy, it locked those settings in.
• The Result: Even with 12 stations in a row (a deep chain), the final station was only off by about 6.66 picoseconds, well within the safety limit.

The Final Scorecard

The team tested their new system in the lab:

• Short distance (1 meter): Synchronized to 3.38 picoseconds.
• Long distance (50 km): Synchronized to 3.92 picoseconds.
• Deep chain (12 stations): Synchronized to 6.66 picoseconds.
• Restarting: The "waking up" error is now 2.82 picoseconds.

Conclusion:
The team successfully built a clock synchronization system that is roughly 5 to 10 times more precise than the previous standard. They achieved this by swapping out noisy analog parts for a clean digital chip, writing a smarter "wake-up" routine, and using an AI-trained conductor to manage the whole network. This ensures that the massive CEPC accelerator can keep its 192 control nodes perfectly in step, allowing for the precise particle collisions needed to study the universe's fundamental secrets.

Technical Summary

Technical Summary: A High-Precision Clock Synchronization System for the CEPC Accelerator

Problem Statement
The Circular Electron Positron Collider (CEPC), a proposed 100 km underground facility in China, requires a timing system capable of distributing a 62.5 MHz reference clock to 192 control nodes with a synchronization precision of 30 ps (standard deviation). While the White Rabbit (WR) protocol is the standard for accelerator timing, the authors identify that the standard WR baseline—typically achieving precision in the range of 20–30 ps over shorter distances—faces critical limitations when scaled to the CEPC's 100 km ring with deep cascading. Specifically, the standard architecture suffers from two primary bottlenecks:

1. Actuation Chain Noise: The traditional control loop relies on an external Digital-to-Analog Converter (DAC) and Voltage-Controlled Crystal Oscillator (VCXO) chain. This analog stage is highly susceptible to power supply ripple and ground noise, and the high-pass nature of the error transfer function allows significant low-frequency VCXO noise to leak through, degrading precision.
2. Restart Uncertainty: Device restarts (due to power cycling or link re-establishment) introduce significant timing uncertainty (88.8 ps peak-to-peak in standard WR) caused by ambiguities in GTX transceiver phase states, FIFO pointer variations, and byte-alignment shifts.

Methodology
The paper presents a comprehensively enhanced WR-based system addressing these limitations through hardware redesign, firmware optimization, and a novel global control architecture.

• Hardware Optimization (Actuation Chain): The external DAC+VCXO actuation chain is replaced by a Silicon Labs Si5345A jitter-attenuating clock generator. This device utilizes a fourth-generation Digital Signal Processing Phase-Locked Loop (DSPLL) and a Digitally Controlled Oscillator (DCO). By moving frequency synthesis and phase control entirely into the digital domain, the system eliminates the board-level analog tuning node. The design employs a custom low-noise crystal oscillator and dedicated Low-Dropout (LDO) regulators to minimize reference and power-supply-induced noise.
• Firmware Optimization (Restart Uncertainty): To mitigate restart-induced timing shifts, the authors implemented a targeted initialization sequence within the FPGA firmware. This includes:
  • TX/RX Phase Alignment: Enabling GTX phase alignment circuits to source clocks directly from the Si5345A, bypassing variable FIFO delays.
  • Manual Byte Alignment: Switching from automatic to manual comma alignment (Bit-Slide) to fix the RX byte boundary to a consistent state.
  • TXOUTCLK Fixing: Using a DDMTD channel to verify and reset the TXOUTCLK phase relative to the local synchronized clock until a consistent state is achieved.
• Global Control Architecture: For multi-node cascading, the authors propose a centralized control system where a PC coordinates phase compensation across all nodes.
  • Temperature Compensation: A feed-forward term is added to the control law, calibrated to a coefficient of −0.76 ps/°C, to compensate for inter-node temperature differences.
  • RL-Based Auto-Tuning: The PID controller gains are auto-tuned using the Twin-Delayed Deep Deterministic Policy Gradient (TD3) reinforcement learning algorithm. The RL agent trains a linear "Actor" network (which mathematically maps to a multi-node PID controller) in a virtual environment before being deployed on the hardware. This approach avoids the computational cost of running RL online while leveraging it for complex parameter optimization.

Key Results
Experimental validation was conducted using a 12-level cascaded system and long-term stability tests.

• Point-to-Point Precision: The system achieved 3.38 ps (1 m fiber), 3.63 ps (30 km), and 3.92 ps (50 km) standard deviation, representing a ~6x improvement over the standard WR baseline.
• Cascaded Performance: In a 12-level cascade, the end-node precision reached 6.66 ps at constant temperature and 7.30 ps under a 13 °C temperature swing. This demonstrates that the global control effectively prevents error accumulation.
• Restart Uncertainty: The optimized firmware reduced restart uncertainty from 88.8 ps (peak-to-peak) to 12 ps (peak-to-peak) and from 14.7 ps to 2.82 ps (standard deviation).
• Jitter and Stability: Synchronized-clock Time Interval Error (TIE) jitter remained below 1 ps RMS regardless of cascade depth. A 4-level cascade operated stably for 25 hours with no lock loss or trend drift.

Significance and Claims
The authors claim that this enhanced system successfully meets the stringent 30 ps synchronization budget required for the CEPC accelerator, providing a margin of safety even in worst-case scenarios (deep cascades with temperature variations). The paper highlights three specific contributions to the field of large-scale accelerator timing:

1. Architectural Shift: Replacing the analog actuation chain with a DSPLL+DCO solution removes the dominant noise source in standard WR nodes, enabling sub-4 ps precision over long distances.
2. Restart Robustness: The firmware-based solution reduces restart uncertainty by a factor of ~7 without requiring additional hardware, solving a historical bottleneck for high-precision applications.
3. Scalable Control: The global control architecture, utilizing RL-tuned gains and temperature feed-forward, demonstrates that a centralized controller can maintain flat precision growth across deep cascades (12 levels) while retaining the determinism required for accelerator operations (by keeping the online controller as a fixed linear PID).

The paper concludes that while laboratory results are promising, future work involves field testing under actual CEPC tunnel conditions (kilometer-scale fibers, distributed temperature gradients) and potential migration of the controller to an embedded FPGA platform for enhanced determinism.