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A Symbolic Neural CPU for Quantization-Simulated Writeback and Interpretable Program Execution

This paper introduces a trace-supervised symbolic neural CPU that combines recurrent control with an explicit operation router and differentiable arithmetic-logic unit bank to enable interpretable, low-precision, and verifiable program execution by exposing detailed state transitions and demonstrating exact reproduction of reference semantics through quantization-simulated writeback.

Original authors: Jose Luis Lima de Jesus Silva

Published 2026-07-14

📖 5 min read🧠 Deep dive

CC BY 4.0

Original authors: Jose Luis Lima de Jesus Silva

Original paper licensed under CC BY 4.0 (http://creativecommons.org/licenses/by/4.0/). ✨ This is an AI-generated explanation of the paper below. It is not written or endorsed by the authors. For technical accuracy, refer to the original paper. Read full disclaimer

Imagine you have a robot chef that can follow a recipe to make a perfect cake. Usually, when we train these AI chefs, we only care if the final cake tastes good. We don't care how they mixed the ingredients, or if they secretly swapped the sugar for salt halfway through, as long as the end result looks like a cake. But what if you need to know exactly what happened in the kitchen? What if you need to audit the process to make sure the robot didn't hallucinate a step?

That's the problem this paper tackles. The authors built a new kind of "Neural CPU" (a brain for a computer) that doesn't just guess the answer; it shows its work, step-by-step, like a student showing their math homework.

The "Show Your Work" Robot Chef

Most AI models are like black boxes: you put data in, and an answer pops out. You can't see the gears turning inside. This new model, called a Symbolic Neural CPU, is different. It's built like a transparent machine with clear, labeled gears.

Here's how it works:

The Recipe (Instructions): The robot gets a list of instructions, like "Add Register A to Register B."
The Gearbox (The Router): Instead of just crunching numbers blindly, the robot has a special switchboard. At every single step, it has to explicitly choose which gear to turn: "Do I add? Do I subtract? Do I multiply?" It has to shout out, "I am choosing the ADD gear!"
The Pantry (Registers): It has a set of numbered jars (registers) holding numbers. It only changes the jar it's supposed to change, leaving the others exactly as they were.
The Audit Trail: Because the robot has to announce which gear it picked and which jar it changed, humans can watch the whole movie of the calculation. They can see if the robot picked the right gear at the right time.

The "Pixelated" Test (Quantization)

The authors wanted to see if this robot could still work if they forced it to use "pixelated" math. Imagine trying to draw a smooth circle using only a grid of big, blocky pixels. This is called quantization. In the real world, computers often use low-precision math to save energy and run faster, but it usually makes things messy and inaccurate.

The authors simulated this by forcing their robot to round its numbers to an 8-bit grid (like a very low-resolution image) before writing the result back to the jar.

The Big Surprise:
Even with this "blocky" math, the robot didn't get confused about which gear to turn.

The Path: The robot chose the correct operation (like ADD or SUBTRACT) 100% of the time for programs up to 1,000 steps long. It never forgot the recipe.
The Numbers: The actual numbers in the jars drifted a little bit because of the "blocky" math. The average error was about 0.002 (a tiny blip in a scale of 0 to 1).
The Fix: The authors realized this drift wasn't a mistake by the robot; it was just the difference between "smooth math" and "blocky math." When they compared the robot's blocky results to a reference robot that also used blocky math, the results matched perfectly. The robot was doing exactly what it was supposed to do; it was just working in a different "resolution."

What This Robot Can't Do (Yet)

It's important to know the limits. The paper explicitly rules out a few things:

It's not a magic mind: The robot is great at following a specific list of instructions it was trained on. But if you hide the instruction (the "opcode") and ask it to guess what to do based only on the numbers, it struggles. If you take away the "Add" label and just show the numbers, the robot gets lost, especially if the task requires remembering things for a long time (like a "memory pressure" test).
It's not a finished hardware chip: The authors are very clear: this is a simulation. They haven't built a physical chip out of silicon yet. They are testing the idea of how such a chip would behave.
It's not a general brain: This robot is specialized for "symbolic execution" (following rules). It's not a general-purpose AI that can write poetry or chat with you.

The "Training Horizon" Limit

The authors also played a fun game with the robot's training. They trained one version of the robot on short recipes (up to 40 steps) and then asked it to cook a massive 1,000-step meal.

The Result: The robot did great for the first 400 steps, but then it started to get confused.
The Cause: It wasn't that the robot was "too small" to handle the big meal. It was that it had never been trained to cook that long. When they retrained a similar robot on longer recipes (up to 160 steps), it could cook the 1,000-step meal perfectly. This suggests the robot's limits are about what it learned, not a hard wall in its brain.

The Bottom Line

This paper introduces a way to build AI that doesn't just give you an answer, but proves how it got there.

The Good News: In these simulations, the robot can follow complex, 1,000-step instructions perfectly, even when forced to use low-precision, "blocky" math. It keeps its logic path clean and auditable.
The Catch: It still needs the instructions to be visible. If you hide the instructions and make it guess, it fails. And right now, this is all happening in a computer simulation, not on a physical device.

Think of it as building a transparent, self-auditing calculator that can run on low-power hardware without losing its mind. It's a promising step toward making AI that we can actually trust to do the math, step by step.

Technical Summary: A Symbolic Neural CPU for Quantization-Simulated Writeback and Interpretable Program Execution

1. Problem Statement

Modern neural networks excel at learning continuous input-output mappings but often function as "black boxes" where internal state transitions are hidden within dense activations or parameters. This opacity makes it difficult to trust learned executors, particularly when the task requires algorithmic reasoning or deployment on constrained hardware. While memory-augmented networks (e.g., Neural Turing Machines) and neurosymbolic approaches have improved reasoning capabilities, they generally lack a register-level audit trail. Specifically, there is a gap in evaluating whether a learned system exposes the specific symbolic operation selected, the exact register updated, and whether the intermediate execution path remains faithful to a reference machine, especially under low-precision (quantized) arithmetic constraints. Current benchmarks often evaluate only final-state accuracy, failing to distinguish between a model that correctly follows an algorithmic path and one that merely approximates the endpoint.

2. Methodology

The authors introduce a trace-supervised symbolic neural CPU, a factorized architecture designed to make the execution process auditable. The system operates on a controlled register-machine interface where the machine state is a register file $r_t \in [0, 1]^{R \times W}$ , and instructions are tuples of an operation and source/destination register indices.

Core Architecture:

Instruction Encoding: Instructions are encoded as one-hot operation labels combined with normalized register indices.
Recurrent Controller: A controller (primarily a GRU, with comparisons to Transformers, TCNs, and State-Space models) processes the instruction and optional memory read vectors to generate hidden states.
Explicit Operation Router: Instead of a monolithic output, the model uses a router to predict logits over a fixed set of named operations ( $O = \{AND, OR, XOR, ADD, SUB, SHL, SHR, MUL\}$ ).
Differentiable ALU Bank: A bank of fixed, differentiable continuous arithmetic and logic operations (e.g., $A_{ADD}(u,v) = \text{clip}(u+v, 0, 1)$ ) generates candidate outputs.
Masked Writeback: The model selects a destination register and updates only that register, preserving the locality constraint of traditional CPUs.
Quantization-Simulated Writeback (QAT8): In the primary experimental setting, the selected ALU output is projected onto an 8-bit fixed-point grid before being written to the destination register.

Training and Evaluation Protocols:

Trace Supervision: The model is trained not just on the final state, but on the complete trajectory of register states, operation labels, and destination masks.
Gumbel-Softmax Relaxation: During training, stochastic operation selection is used to allow gradient flow. During evaluation, deterministic hard argmax gates are used to ensure an inspectable, symbolic execution path.
Matched Fixed-Point Replay: To evaluate low-precision performance, the authors define a "matched replay" reference. This is an independent, fixed-point reimplementation of the reference interpreter executed at the same 8-bit precision as the model. This separates "reference semantics mismatch" (drift due to quantization) from "execution failure" (wrong operations).
Benchmarks: The system is evaluated on synthetic programs of varying lengths (up to 1000 instructions), widths (16 and 32 registers), and task families including visible-opcode execution, hidden-opcode memory pressure, and equivalent-program energy-choice tasks.

3. Key Contributions

Auditable Execution Interface: The paper establishes a framework where the execution process is decomposed into inspectable components: operation gates, destination masks, register trajectories, and memory signals.
Quantization-Simulated Writeback with Matched Replay: The authors demonstrate that a neural executor can preserve the symbolic operation path exactly even when numerical values drift due to 8-bit quantization, provided the evaluation uses a matched low-precision reference rather than a full-precision continuous reference.
Factorized Architecture Design: The work shows that separating the controller, operation router, and fixed ALU bank is necessary for interpretable execution. Ablations reveal that removing gate supervision leads to uninterpretable latent paths, even if final accuracy is maintained.
Extended Interfaces: The framework is extended to include ValueMemory (for hidden-opcode tasks), spiking controllers (using leaky integrate-and-fire dynamics for control memory only), and a semantic bridge to RV32I base-integer instructions.

4. Results

Length Stability and Logical Correctness: On the principal 16-wide register profile, the non-quantized executor reproduces reference execution exactly. The 8-bit quantization-simulated (QAT8) executor preserves the symbolic operation path (gate agreement) at 100% for programs up to 1000 instructions, despite continuous-register numerical drift (Final MAE $\approx 2.5 \times 10^{-3}$ ).
Matched Replay Faithfulness: When evaluated against the matched fixed-point replay (the 8-bit reference), the QAT8 executor achieves 100% scalar-grid faithfulness and zero trace error. This confirms that the observed drift in continuous scoring is a reference-semantics mismatch, not an execution failure.
Architecture Comparisons: Recurrent controllers (GRU) generally outperform or match Transformers and other variants on these tasks. Crucially, ablations show that removing the explicit gate supervision loss causes gate agreement to collapse (to ~74.5%), even if the model learns to approximate the final state.
Memory Pressure and Hidden Opcodes: When opcode cues are hidden (memory-pressure tasks), performance degrades significantly, exposing the limits of delayed state use and temporal binding. ValueMemory variants improve performance on stack-like tasks but struggle with long hidden-memory reversals.
Extrapolation Limits: A 32-wide profile trained on short programs (max 40 steps) fails to generalize to long horizons (beyond ~500 steps), showing that the limit is the training horizon, not the state width. Retraining on longer horizons restores exactness.
Cost-Aware Execution: The model successfully learns to select lower-cost equivalent programs (min-energy paths) when trained with energy-choice objectives, reducing proxy energy by ~38% while maintaining correctness.

5. Significance and Claims

The paper claims to establish a trace-verifiable framework for interpretable, low-precision, and controllable neural execution. Its primary significance lies in shifting the evaluation paradigm from "endpoint accuracy" to "transition-level faithfulness."

The authors modestly claim that their results demonstrate:

Audibility: Learned executors can be designed to expose their internal symbolic choices (operations and register updates) rather than hiding them in continuous states.
Low-Precision Robustness: Neural executors can maintain logical correctness (symbolic path) even when numerical precision is constrained to 8-bit, provided the evaluation metrics account for quantization semantics.
Control: The framework supports extensions for closed-loop control and hardware-aware constraints (energy/delay proxies).

The paper explicitly states it does not claim to be a physical processor implementation, a full integer-only inference engine, or a complete RISC-V compliant emulator. Instead, it serves as a semantic bridge and a diagnostic substrate to verify whether learned systems preserve the stepwise machine trace required for trustworthy deployment in device-facing runtimes. The work highlights that for neural systems to function as co-processors or controllers, their operation choices and state transitions must be visible and verifiable before hardware deployment.